Substrate bias generator

Details Substrate bias generator Substrate bias generator

1980-07-23

1983-05-17

Munson, Gene M.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307296R, 307297, 357 41, 357 23, H03K 3353, H03K 301, H01L 2978, H01L 2702

Patent

active

043842186

ABSTRACT:
A substrate bias generator which includes: an MOS capacitor having an electrically insulating film located between two electrodes, one of which is disposed on one main face of a P.sup.- semiconductor substrate; and first, second and a third N.sup.+ semiconductor regions disposed in a spaced relationship on that main face. The first and second regions form a grounded source and a drain of an MOSFET having a gate connected to both the drain and the other electrode of the capacitor. The second and third regions form a source and a drain of another MOSFET having a gate connected to both the drain and the other main face of the substrate. A train of square pulses is supplied to the one electrode of the capacitor.

REFERENCES:
patent: 3794862 (1974-02-01), Jenne
patent: 4115794 (1978-09-01), De La Moneda
patent: 4142114 (1979-02-01), Green
patent: 4255677 (1981-03-01), Boonstra et al.
patent: 4255756 (1981-03-01), Shimotori et al.
Pashley et al., "A 70-ns 1K MOS RAM", IEEE Int. Solid-State Circuits Conf. (2/76), Dig. Tech. Papers, pp. 138-139, 238.

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