Substrate bias generator

Details Substrate bias generator Substrate bias generator

1980-06-30

1982-06-22

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307304, H03L 100, H03K 3354, H03K 3017

Patent

active

043364667

ABSTRACT:
A substrate bias generator for an integrated circuit, metal-oxide-semiconductor (MOS) random access memory (RAM) is described. The on-chip generator includes two input terminals for receiving first and second trains of periodic pulses. The periodic pulses have the same frequency and are phase synchronized. However, the first train of pulses has a greater duty cycle than the second train of pulses. Amplitude transitions associated with the first and second trains of pulses are capacitively coupled to first and second nodes, respectively. A pair of transistors are coupled to the nodes, one transistor for clamping the first node to ground when the second node receives a positive-going voltage transition, and another transistor for selectively coupling amplitude transitions from the first node to the second node. In operation, both nodes are driven more negative with each successive incoming pulse until they reach about -5 volts for the case in which the amplitude of the incoming pulses is 5 volts. A third transistor closes a current path between the first node and the chip's substrate when the substrate voltage is at least one threshold voltage more positive than the first node voltage. As a result, the substrate voltage is driven to a negative level which is about one threshold voltage more positive than the furthest negative voltage level on the first node.

REFERENCES:
patent: 4142114 (1979-02-01), Green
patent: 4208595 (1980-06-01), Gladstein et al.
patent: 4229667 (1980-10-01), Heimbigner et al.
Blaser et al., "Substrate and Load Gate Voltage Compensation"; Session VI: MOS Techniques; 1976 IEEE-ISSCC; 2/18/76; Digest of Technical Papers pp. 56-57.
Gladstein et al., "FET Substrate Generator Derived from Low Voltage Power Supply"; IBM Tech. Discl. Bull.; vol. 21, No. 12, pp. 4935-4936; 5/1979.

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