Substrate bias circuit having substrate bias voltage clamp and o

Details Substrate bias circuit having substrate bias voltage clamp and o Substrate bias circuit having substrate bias voltage clamp and o

1988-06-06

1990-02-27

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307304, H03K 301, H03K 3353

Patent

active

049048856

ABSTRACT:
A substrate bias circuit controls application of a conventional substrate charge pump to the substrate of a semiconductor integrated circuit to prevent latching up of parasitic transistors at the time of turn on of power to the integrated circuit. The substrate bias circuit comprises a filed effect transistor having its source and drain electrodes connected between substrate and charge pump. The gate electrode of the transistor is driven through an RC circuit by the power supply to turn on the transistor for a predetermined time period at the time power is initially applied to the integrated circuit. There is no latching up of the parasitic transistors because application of positive bias voltage to the substrate during turn-on is prevented.

REFERENCES:
patent: 3940747 (1976-02-01), Kuo t al.
patent: 4439692 (1984-03-01), Beekmans et al.
patent: 4631421 (1986-12-01), Inoue et al.
patent: 4670668 (1987-06-01), Liu
patent: 4798974 (1989-01-01), Reczek et al.
IEDM 1985: "Status and Transient Latch-Up Hardness in N-Well On-Chip Substrate Bias Generator", by D. Takacs et al., 18.5, 1985, pp. 504-508.

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