Substrate bias circuit

Details Substrate bias circuit Substrate bias circuit

1980-02-12

1983-03-22

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200B, 307304, 357 48, 357 51, 357 23, H01L 2978, H01L 2704

Patent

active

043777562

ABSTRACT:
An insulated gate field-effect transistor (MOS.multidot.FET) formed as a basic element of an integrated circuit formed together with a substrate bias circuit in a semiconductor substrate having negative potential. In the substrate bias circuit, semiconductor regions (p.sup.+ -regions) having impurity concentrations higher than that of the semiconductor substrate (p-type) are formed between the semiconductor regions (n.sup.+ -region) and the semiconductor substrate (p-type) to form n.sup.+ p.sup.+ p-diodes.

REFERENCES:
patent: 3794862 (1974-02-01), Jenne
patent: 4164751 (1979-08-01), Tasch, Jr.
patent: 4255756 (1981-03-01), Shimotori et al.
Pashley et al., "A 70-ns 1K MOS RAM", 1976 IEEE International Solid State Service Conference, (pp. 138,139,238).

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