Substrate and production method thereof

Details Substrate and production method thereof Substrate and production method thereof

1998-03-24

2001-04-24

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

C438S458000, C216S002000, C216S033000, C148S033000, C117S104000

Reexamination Certificate

active

06221738

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for producing a semiconductor substrate, and more particularly a method for producing a semiconductor substrate adapted for the formation of an electronic device or an integrated circuit in a single-crystal semiconductor layer on a dielectric separation layer or an insulator, or in a single-crystal compound semiconductor on an Si substrate.
2. Related Background Art
The formation of a single-crystal Si semiconductor layer on an insulator is widely known as semiconductor-on-insulator (SOI) technology, and various research has been made because the device utilizing the SOI technology has various advantages that cannot be attained with the use of a bulk Si substrate in the preparation of ordinary Si integrated circuits. More specifically, the use of the SOI technology provides the following advantages:
1. dielectric separation can be easily conducted to attain a higher degree of integration;
2. radiation resistance is excellent;
3. stray capacitance can be reduced to attain a higher speed;
4. a well forming step can be omitted;
5. latch-up can be prevented; and
6. a fully depleted field effect transistor can be made by thin film formation.
These features are detailed, for example, in Special Issue:
“Single-crystal silicon on non-single-crystal insulators”, edited by G. W. Cullen, Journal of Crystal Growth, Vol. 63, No. 3, pp.429-590 (1983).
Also in recent years, many reports have been published on the SOI substrate for realizing higher speed and lower power consumption in the MOSFET (IEEE SOI conference 1994). Also use of the SOI substrate allows for the shortening of device process steps, since the presence of an insulator layer under the device simplifies the device isolation process in comparison with the case of device formation on a bulk Si wafer. Thus, in comparison with the MOSFET or IC formed on bulk Si, a total reduction of the wafer cost, and the process cost together with a higher performance, is expected.
In particular, the fully depleted MOSFET is expected to achieve higher speed and lower power consumption by improvement of a driving power. The threshold voltage (V+h) of the MOSFET is generally determined by the impurity concentration of the channel portion, and in case of the fully depleted MOSFET utilizing the SOI structure, the thickness of the depletion layer is also affected by the film thickness of SOI. Consequently, in order to produce large-area integrated circuits with high production yield, there has strongly been desired uniformity of SOI film thickness.
Also the devices formed on the compound semiconductor have excellent features, such as high speed or light emission, which are not achievable with the silicon substrate. Presently such devices are mostly formed by epitaxial growth on a compound semiconductor substrate such as GaAs or the like. However, such a compound semiconductor substrate has drawbacks related to expense, low mechanical strength, difficulty of preparation of a large area wafer and the like.
In view of such a situation, there has been made an attempt to heteroepitaxially grow a compound semiconductor on the silicon wafer which is inexpensive, mechanically strong and can be easily prepared with a large area.
Investigations on the formation of the SOI substrate have been active since the 1970's. In the initial period, there have been investigated a method of heteroepitaxially growing a single-crystal silicon on an insulating sapphire substrate (SOS: silicon on sapphire) and a method of forming the SOI structure by dielectric separation utilizing oxidation of porous Si (FIPOS: full isolation by porous oxidized silicon).
The FIPOS method consists of forming islands of n-type Si layer on the surface of a p-type single-crystal Si substrate by proton implantation (Imai et al., J. Crystal Growth, Vol. 63, 547 (1983)) or by epitaxial growth and patterning, then making only the p-type Si substrate porous by anodizing in HF solution so as to surround the Si islands from the surface side and achieving dielectric isolation of the n-type Si islands by accelerated oxidation. Since in this method the isolated Si islands are determined prior to the device manufacturing step, the freedom of device designing may be limited.
An oxygen ion implantation method referred to as the SIMOX method was originally reported by K. Izumi. After oxygen ions are implanted with a concentration of 10
17
to 10
18
/cm
2
into an Si wafer, it is annealed at a high temperature of about 1320° C. in an argon-oxygen atmosphere, whereby the implanted oxygen ions combine with Si atoms around a depth corresponding to the projected stroke (Rp) of the ion implantation to form a silicon oxide layer. In this operation, a Si layer present on the oxidized silicon layer and made amorphous by oxygen ion implantation recrystallizes to form a single-crystal silicon layer. The number of defects in the surface Si layer was as high as 10
5
/cm
2
, but has been reduced to about 10
2
/cm
2
by maintaining the implanted amount of oxygen ions at about 4×10
17
/cm
2
. However, since the implantation energy and the implantation amount are limited to a narrow range in order to maintain desired film quality of the Si oxide layer and desired crystallinity of the surface Si layer, the thicknesses of the surface Si layer and the buried Si oxide (BOX: buried oxide) layer have been limited to specified values. Therefore, for obtaining the surface Si layer of a desired film thickness, it has been necessary to effect sacrifice oxidation or epitaxial growth. In such a case, there is a problem that the uniformity of the film thickness inevitably deteriorates, since the deterioration of the uniformity of the film thickness due to such a process is added to the original film thickness distribution.
It has also been reported that the BOX layer contains a region, called “pipe”, of defective Si oxide formation. One of the causes of such a defective formation is foreign matter such as dust at the implantation. In the portion of such a pipe, there is generated a leak between an active layer and a supporting substrate which deteriorates the device characteristics.
The ion implantation of the SIMOX method with a larger amount of implantation in comparison with that in the ordinary semiconductor process requires a long implantation time even when using an apparatus developed exclusively for this purpose. Since the ion implantation is conducted by rester scanning with an ion beam of a predetermined current or by expanding an ion beam, it is anticipated to require a longer time with an increase in the area of the wafer. Also the high-temperature heat treatment of a wafer having a large area is anticipated to become more difficult, because of the generation of problems such as slip due to the temperature distribution within the wafer. As the SIMOX method requires a heat treatment at 1300° C. or higher which is not usually employed in the Si semiconductor process, there is concerned an increase in the problems to be solved such as apparatus development, metal contamination and slip.
In addition to the conventional SOI forming methods described above, there is recently contemplated a method of bonding a single-crystal Si substrate to another thermally oxidized single-crystal Si substrate by heat treatment or with an adhesive to obtain the SOI structure. In this method, an active layer for device formation has to be formed as a uniform thin film. Stated differently a single-crystal Si substrate of a thickness of several hundred micrometers has to be formed as a thin film on the order of a micrometer or less. This formation of the thin film is conducted by three methods as described below:
1. thin film formation by polishing
2. thin film formation by local plasma etching
3. thin film formation by selective etching.
By the above method 1, it is difficult to provide a uniform thin film by polishing. In particular, fluctuation in thickness becomes as high as several tens of percent when forming a thin film of submicron

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