Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2000-11-08
2002-08-13
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S311000
Reexamination Certificate
active
06432792
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention:
The present invention is directed generally to the field of device insulation and more specifically to a substrate and a method for manufacturing a substrate especially for SOI technologies.
Description of the Related Art:
Semiconductor devices, especially silicon devices, have problems with inherent parasitic circuit elements due to junction capacitances. One way to circumvent the problem is to fabricate semiconductor devices on an insulating substrate. One of the initial approaches was to grow silicon epitaxially on a substrate of sapphire (called silicon-on-sapphire, or SOS). A more recent approach is the so called silicon-on-insulator (SOI) technology. The components or devices are thereby realized in a SOI substrate. A SOI substrate normally has an insulating layer of SiO
2
on a single-crystal silicon wafer and a single-crystal silicon layer on the insulating layer. This single-crystal silicon layer is the surface of the SOI substrate. The insulating layer of the SOI substrate assures the vertical insulation, whereas the lateral insulation of the components is realized for example by trenches filled with insulating material or local oxidation of silicon (LOCOS).
The advantages of the silicon-on-insulator technology are widely recognized: higher circuit speed, lower power consumption, greater immunity to radiation-induced errors, and compatibility with existing IC fabrication processes. However, the consistency and cost of the SOI substrates and their availability remains a problem. In order to form SOI substrates, any of a variety of methods may be used, see for example “Thin-film SOI merges” by M. L. Alles, IEEE Spectrum 35 Magazine, June 97, pages 37 to 45. In the prior art, the main manufacturing options are the so called “separation by implantation of oxygen” (Simox) and the so called “wafer bonding”, each with a number of process variants.
The Simox process produces a SOI substrate by first implanting a silicon substrate with a relatively high dose of oxygen ions and then performing a high temperature anneal at about 1300° C. for several hours, in order to form a buried layer of silicon oxide. The wafer bonding process is a method of producing SOI substrates in which two silicon wafers each with oxide on the surface, are bonded together and annealed at temperatures higher than 800° C. to strengthen the bond. The bulk of one of the two wafers is then removed by any of several methods—grinding, etching, or polishing, for example.
Unfortunately, the conventional SOI technologies are quite expensive to realize. Therefore, SOI substrate prices typically are several times those of bulk silicon substrates, preventing SOI substrates from being used in cost-sensitive applications as low-end consumer electronics and DRAMs.
Accordingly, there is need for a new, simpler and more economical way of achieving circuit size reductions, speed improvements, and power reduction-operation at lower voltage.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an a method for manufacturing a substrate for SOI technologies and a substrate produced by the method which overcomes the above-mentioned disadvantageous of the prior art apparatus and methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention a method of producing a substrate that includes steps of:
a) providing a semiconductor wafer, having a front side where active devices are to be located or are located and a back side opposite to the front side;
b) producing at least a trench in the back side of the wafer, the trench extending from the back side of the wafer to a level having a predetermined distance from the front side of the wafer; and
c) producing an insulation structure in the trench, so that a vertical insulation for active devices located on the front side of the wafer is provided.
In accordance with an added feature of the invention, step c) of producing an insulation structure in the trench includes filling the trench with insulating material, or providing the surfaces inside the trench with a layer made of insulating material. Preferably, the insulating material is selected from the group consisting of SiO
2
and Si
3
N
4
.
In case the sidewalls of the trench are provided with a layer made of insulating material, it is preferred that the remaining part of the trench is filled with a fill suitable of providing mechanical stability, preferably a silicon fill or a metal fill.
In case the remaining part of the trench is to be filled with a silicon fill, it is preferred that the filling is done by the deposition and re-etching of a silicon layer.
In accordance with an additional feature of the invention, the trench is produced by etching the wafer using a trench mask. The trench mask preferably has a layer sequence with a lower layer of thermal SiO
2
, a middle layer of CVD Si
3
N
4
and an upper layer of CVD SiO
2
.
For reasons of mechanical stability it is also preferred that the step b) of producing at least one trench and the step c) of producing an insulating structure are repeated until a predetermined percentage of the back side of the wafer is made of the insulating structure.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a substrate and method for manufacturing the same, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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patent: 5599722 (1997-02-01), Sugisaka et al.
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patent: 6013933 (2000-01-01), Foerstner et al.
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Michael L. Alles: “Thin-film SOI emerges”, IEEE Spectrum, Jun. 1997, pp. 37-45.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Nelms David
Nhu David
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