Subsampling digitizer-based frequency synthesizer

Details Subsampling digitizer-based frequency synthesizer Subsampling digitizer-based frequency synthesizer

2000-03-14

2003-08-05

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S012000, C331S016000, C375S376000, C327S107000, C327S159000, C327S156000

Reexamination Certificate

active

06603362

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to communication systems, and is particularly directed to a new and improved digitally controlled frequency synthesizer that employs a subsampling digitizer to downconvert the synthesizer's output frequency to baseband for precision tuning of the synthesizer's output frequency in a digitally controlled phase locked loop.
BACKGROUND OF THE INVENTION
FIG. 1
diagrammatically illustrates a conventional frequency synthesizer that employs a phase locked loop (PLL)
10
operating at a relatively low band (e.g., baseband), to stably tune the output frequency f
O
of the synthesizer in accordance with a precision reference frequency f
R
. The reference frequency f
R
is subdivided by a divider
12
down to a reduced frequency value f
&PHgr;
associated with baseband operation of the loop's phase detector
14
. A second input to the phase detector
14
is obtained by a division by N of the output of a voltage controlled oscillator (VCO)
16
down to the phase detector's operating frequency f
&PHgr;
. The control voltage for the VCO is supplied by a loop filter
15
coupled to the output of the phase detector
14
.
Division by N of the output of a voltage controlled oscillator (VCO)
16
down to the phase detector's operating frequency f
101
is typically implemented by coupling the output frequency f
O
to a first (divide-by-N
1
) frequency divider
17
, which is coupled in cascade with a second (divide-by-N
2
) frequency divider
18
within the phase locked loop
10
. The first frequency divider
17
provides a relatively coarse division of the output frequency f
O
down to a value that may be incrementally further divided in ‘tuning’ steps associated with the adjustment of the synthesizers's output frequency provided by the PLL's internal divider
18
. The composite division of the output frequency f
O
by divisors N
1
and N
2
is reflected in a complementary multiplication of the phase noise by the output voltage from the phase detector
14
which drives the VCO
16
in accordance with the relationship 20logN. This means that as the output frequency increases and the step size decreases, N and therefore phase noise degradation will increase.
One way to reduce the value of N is to install analog signal-based down-conversion components in the feedback path from the VCO through the divider components to the phase detector. This serves to provide a precursor reduction in frequency of the signal fed back to the phase locked loop from the output of the VCO, so that the overall magnitude of the divisor N may be reduced, and thereby decrease the phase noise multiplication figure defined by 20logN. This precursor analog-based downconversion technique is shown diagrammatically in
FIG. 2
, wherein the output of the VCO
16
is multiplied by a local oscillator signal f
LO
in a mixer
21
, to produce an intermediate frequency signal f
I
. This intermediate frequency f
I
is then filtered in a band pass filter
23
and coupled through the frequency divider
17
to the internal frequency divider
18
of the PLL
10
.
Because the input frequency f
I
to the frequency divider
17
is lower than that (f
O
) in the architecture of
FIG. 1
, the overall or composite magnitude N′ of the cascaded frequency dividers
17
and
18
may be smaller than that of FIG.
1
. This means that the resultant phase noise multiplication value of 20logN′ of the architecture of
FIG. 1
is smaller than the value of 20logN, so that a reduction in phase noise degradation relative to the scheme of
FIG. 1
is realized. However, for proper operation, the analog architecture of
FIG. 2
requires extremely high precision and low leakage analog downconverter components, which increases complexity and cost.
SUMMARY OF THE INVENTION
In accordance with the present invention, both the fundamental phase noise multiplication problem of the architecture of FIG.
1
and the cost of implementation problem of the analog down-conversion scheme of
FIG. 2
are substantially mitigated by replacing the frequency division components of the feedback paths of the architectures of
FIGS. 1 and 2
with a subsampled analog-to-digital converter. By clocking the analog-to-digital converter at a subsampling frequency which has a subharmonic relationship with the output frequency of the VCO, two benefits are obtained.
First, the subsampling digitizing operation performs ‘constructive aliasing’ of the oscillator output frequency, so that at some value of the subharmonic ratio, the Nyquist window of the convolved output of the digitizer includes the baseband reference frequency f
&PHgr;
for the phase locked loop. Secondly, the digitally controlled synthesizer's phase locked loop uses digital components for tuning control, so that no additional phase noise division is employed. This means that only the value of the subsampling ratio ‘n’ of the subsampling clock to the analog-to-digital converter will determine the magnitude of the multiplicative phase noise error (20logn).
In accordance with a non-limiting example of a quadrature channel-based phase locked loop, a precision reference frequency signal is coupled to a processor-controlled baseband oscillator, which produces in-phase (I) and quadrature-phase (Q) reference frequency step-controlling components that are applied to respective in-phase and quadrature channels of a quadrature phase detector, within a digitally controlled phase locked loop. The use of a digitally controlled phase locked loop enables the stepsize of the synthesizer output to be controlled in very refined (sub-Hertz) values.
I and Q channels of the quadrature phase detector are also coupled to the output of a subsampled analog-to-digital converter, to which the output frequency of a (voltage or current) controlled oscillator that produces the synthesizer's output frequency is coupled. The outputs of the I and Q channels of the quadrature phase detector are coupled through respective digital low pass filters to a phase error generator, which outputs a phase error signal. The phase error signal is coupled through a digital loop filter to a digital-to-analog converter, the analog output of which sets the output frequency of the controlled oscillator and thereby the synthesizer.


REFERENCES:
patent: 5444420 (1995-08-01), Wernlund
patent: 5838749 (1998-11-01), Casper et al.
patent: 6252464 (2001-06-01), Richards et al.

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