Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor
Reexamination Certificate
2010-02-25
2011-12-27
Luu, Chuong A. (Department: 2892)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
C257S623000, C257S624000, C257S626000
Reexamination Certificate
active
08084845
ABSTRACT:
Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.
REFERENCES:
patent: 6057580 (2000-05-01), Watanabe et al.
patent: 6222225 (2001-04-01), Nakamura et al.
patent: 6417047 (2002-07-01), Isobe
patent: 6720610 (2004-04-01), Iguchi et al.
patent: 6767813 (2004-07-01), Lee et al.
patent: 6911697 (2005-06-01), Wang et al.
patent: 6974746 (2005-12-01), Iguchi et al.
patent: 7041558 (2006-05-01), You et al.
patent: 7074623 (2006-07-01), Lochtefeld et al.
patent: 7183615 (2007-02-01), Yamashita et al.
patent: 7382015 (2008-06-01), Iguchi et al.
patent: 7396720 (2008-07-01), Sandhu et al.
patent: 7488646 (2009-02-01), Iguchi et al.
patent: 7524747 (2009-04-01), You et al.
patent: 7582928 (2009-09-01), Iguchi et al.
patent: 2002/0011612 (2002-01-01), Hieda
patent: 2002/0140039 (2002-10-01), Adkisson et al.
patent: 2003/0129845 (2003-07-01), Cabuz et al.
patent: 2004/0150037 (2004-08-01), Katsumata et al.
patent: 2004/0262687 (2004-12-01), Jung et al.
patent: 2005/0104091 (2005-05-01), Tabery et al.
patent: 2005/0136617 (2005-06-01), Jang
patent: 2005/0167754 (2005-08-01), Kang et al.
patent: 2005/0173768 (2005-08-01), Lee et al.
patent: 2005/0255643 (2005-11-01), Ahn et al.
patent: 2005/0285509 (2005-12-01), Funamoto et al.
patent: 2006/0105578 (2006-05-01), Hong et al.
patent: 2007/0287259 (2007-12-01), Kavalieros et al.
patent: 1655365 (2005-08-01), None
Ruge, I. and Mader, H., “Halbleiter-Technologie” Springer Verlag, Berlin, pp. 212-215 (1991).
Chinese Office Action issued Nov. 27, 2009 in corresponding Patent Application No. 200780025866.6.
International Search Report issued Nov. 5, 2007 in corresponding PCT Application No. PCT/US2007/015146.
Fischer Mark
Hanson Robert J.
Torek Kevin J.
Knobbe Martens Olson & Bear LLP
Luu Chuong A.
Micro)n Technology, Inc.
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