Subranging ADC with error correction through increased fine step

Details Subranging ADC with error correction through increased fine step Subranging ADC with error correction through increased fine step

1990-09-17

1992-03-24

Williams, Howard L.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341154, 341158, H03M 114

Patent

active

050992406

ABSTRACT:
A multiple-clock-cycle subranging type A/D converter utilizing sufficient fine steps in the LSB identification to cover two complete coarse steps so that there are no gaps in the fine steps and no potential errors. Also, two LSB encoders can be utilized, one during each clock cycle, to increase the speed of the A/D converter. The components of the A/D converter are positioned on a semiconductor chip so that noise from electronic switches is not introduced into the reference voltage ladder.

REFERENCES:
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patent: 4568910 (1986-02-01), Sekino et al.
patent: 4599599 (1986-07-01), Sekino et al.
patent: 4612531 (1986-09-01), Dingwall et al.
patent: 4635036 (1987-01-01), Yoshizawa
patent: 4733217 (1988-03-01), Dingwall
patent: 4745393 (1988-05-01), Tsukada et al.
patent: 4849759 (1989-07-01), Hughes
patent: 4903028 (1990-02-01), Fukushima
patent: 4912470 (1990-03-01), Hosotani et al.

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