Subchannel doping to reduce short-gate effects in field effect t

Fishing – trapping – and vermin destroying

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357 233, 357 24, 357 91, 437 29, 437912, H01L 21265, H01L 21324

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047881569

ABSTRACT:
One embodiment of a process in accordance with our invention includes the step of forming a P type region on a semiconductor substrate. After the P type region is formed, an N type layer is epitaxially grown on the P type region. A Schottky gate is then formed on the N type epitaxial layer. A first portion of the epitaxial layer serves as a transistor source, a second portion of the epitaxial layer serves as the transistor drain, and a third portion of the epitaxial layer serves as the channel. Of importance, the P type semiconductor region helps prevent various short channel effects caused when current carriers flowing between the source and drain flow too far from the Schottky gate.

REFERENCES:
patent: 4377030 (1983-03-01), Pettenpaul et al.
patent: 4422087 (1983-12-01), Ronen
patent: 4503599 (1985-03-01), Ueyanagi et al.
patent: 4642879 (1987-02-01), Kawata et al.
Takada et al., "A 2 Gb/s Throughput GaAs Digital Time Switch LSI Using LSCFL", IEEE 1985 Microwave and Millimeter Wave Monolithic Circuit Symposium at St. Louis, MO, pgs. 22-26.
Yamasaki et al., "Below 10 ps/Gate Operation With Buried p-Layer SAINT FETS", published in Electronics Letters on Dec. 6, 1984, pp. 1029-1031.

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