Sub word line driving circuit and a semiconductor memory device

Details Sub word line driving circuit and a semiconductor memory device Sub word line driving circuit and a semiconductor memory device

1997-07-02

1998-11-10

Mai, Son

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518911, G11C 700, G11C 800

Patent

active

058354395

ABSTRACT:
A sub word line driving circuit for driving a sub word line is used for a semiconductor memory device having a hierarchical word line structure. The sub word line driving circuit includes two NMOS transistors for driving the sub word lines to reduce an area of overall memory device when being applied to a VLSI memory device of Gigabit class while there is no time loss caused by delay between driving signals heretofore required in a bootstrap process to involve high operating speed and to be favorable in a reliability aspect of the device.

REFERENCES:
patent: 5253202 (1993-10-01), Bronner et al.
patent: 5317538 (1994-05-01), Eaton, Jr.
patent: 5416748 (1995-05-01), Fujita
patent: 5426333 (1995-06-01), Maeda
patent: 5467316 (1995-11-01), Kim
patent: 5506816 (1996-04-01), Hirose
patent: 5519665 (1996-05-01), Chishiki
patent: 5587959 (1996-12-01), Tsukude

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