Sub-word line driver circuit for memory blocks of a semiconducto

Details Sub-word line driver circuit for memory blocks of a semiconducto Sub-word line driver circuit for memory blocks of a semiconducto

1996-12-16

1998-06-02

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 365190, 365 51, 365 63, G11C 800

Patent

active

057611483

ABSTRACT:
A block selecting scheme for a memory device. The block selecting scheme includes a sub word line driver circuit having multiple sub word line drivers and an inverter circuit. For one embodiment, the sub word line driver circuit includes four sub word line drivers. Each sub word line driver is used to select the sub word line for a corresponding memory block. Each of the sub word line drivers is coupled to a global word line via the inverter circuit. Furthermore, each of the sub word line drivers operates as an inverter. By coupling the global word line and each of the sub word lines via two inversion circuits, the global word line and the sub word lines are typically at the same voltage level. Thus, the deleterious effect of shorting between adjacent global word lines and sub word lines is substantially reduced. Furthermore, by grouping more than two sub word line drivers together, the overall die size of the memory device may be reduced.

REFERENCES:
patent: 5193074 (1993-03-01), Anami
patent: 5416748 (1995-05-01), Fujita
patent: 5461593 (1995-10-01), Kim
"Session XIII: Static RAMs, THPM 13.3: A 25ns Full-CMOS 1Mb SRAM", IEEE International Solid-State Circuits Conference, pp. 178-179, Feb. 18, 1988.
"Session 8: Static RAMs, TPM 8.1: A 15NS 4MB CMOS SRAM", IEEE International Solid-State Circuits Conference, pp.126-127 & p. 280, Feb. 15, 1990.

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