Sub row decoder circuit for semiconductor memory device

Details Sub row decoder circuit for semiconductor memory device Sub row decoder circuit for semiconductor memory device

1997-12-29

1999-08-03

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518906, 36518907, 36518911, G11C 800

Patent

active

059333880

ABSTRACT:
A sub row decoder circuit for a semiconductor memory device, comprising a bootstrap transistor connected between a pull-up signal input node and a bootstrap node, a pull-up transistor connected between a word line boosting signal line and a word line, a switching transistor connected between the pull-up signal input node and a first node, and a pull-down transistor connected in the form of a diode between the first node and the word line. The bootstrap transistor has its gate for inputting a voltage signal, and the pull-up transistor has its gate connected to the bootstrap node. The switching transistor has its gate for inputting an inverted one of a pull-up signal at the pull-up signal input node. According to the present invention, a source of the pull-down transistor is connected not to a ground voltage but to the pull-up signal, thereby making layout and processing ready. Further, the pull-up signal and a pull-down signal have the same voltage level in a standby mode, thereby preventing a standby current from being increased although metal lines are short-circuited.

REFERENCES:
patent: 5506816 (1996-04-01), Hirose et al.
patent: 5717650 (1998-02-01), Chung et al.
patent: 5808955 (1998-09-01), Hwang et al.
patent: 5818790 (1998-10-01), Kim et al.

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