Sub-ranging analogue to digital converter using differential sig

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Patent

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Details

341122, H03M 114

Patent

active

053132068

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

This invention relates to analogue to digital converters, and more particularly to such converters which operate on differential signals.


BACKGROUND OF THE INVENTION

One of the major problems with converters of the kind described implemented in monolithic (integrated circuit) form results from inherent errors within the components of the circuit. For example, the sample and hold stage generally incorporates a solid state switch to enable the input analogue signal to be samples. When such a switch is operated there is always charge breakthrough from the switch logic drive to the hold capacitor. This can be a very serious source of error and efforts are made to minimise it. These usually require the provision of very good switches (e.g. MOSFET or JFET) and a large hold capacitor. Since bipolar IC processes are more suited to high speed analogue circuitry, the requirement for FET devices complicates the process. Furthermore, since the hold capacitor needs to be large, it must either be sited off the chip on which the other components are provided or it will occupy a very large area of the chip. A further problem is that any input bias current required by the output amplifier of the sample and hold circuit discharges the hold capacitor and so the output "droops" with time. Another problem is that conventional analogue to digital conversion stages, for example flash converters, have a rather different structure from the sample and hold circuit leading to difficulties with variations in processing times.
Problems have also arisen with the second analogue to digital conversion stage. Conventionally, these have made use of high gain amplifiers with feed back around them to provide the necessary gain. While the signal is being acquired for the first conversion stage, the inputs to this feed back amplifier may be as large as the full input range of the converter, consequently the output of the amplifier will be driven into saturation. Gain switching and clamping stages are usually employed with these amplifiers to avoid this.
EP-A-0311105 describes an analogue to digital converter which includes a flash converter but which operates on a feed back principle and suffers from the problems described above in connection with inherent errors. WO-A-90/03066 also discloses a flash converter but again this suffers from the disadvantages described above.


SUMMARY OF THE INVENTION

In accordance with the present invention, an analogue to digital converter of the kind described is characterised in that the sample and hold stage and the first and second analogue to digital conversion stages each responds to a respective pair of differential input signals; in that each of the sample and hold and digital to analogue conversion stages generates output signals in the form of differential pairs of currents; and in that the difference means arithmetically combines appropriate pairs of the currents from the sample and hold and digital to analogue conversion stages to generate a differential current pair for input to the second analogue to digital conversion stage.
The invention relates to an analogue to digital converter of the kind comprising a first analogue to digital conversion stage for performing a relatively coarse conversion on a sample of an analogue input signal; a sample and hold stage for holding the sample of the analogue signal fed to the first conversion stage while it is converted by the first conversion stage; a digital to analogue conversion stage to which the digital output from the first conversion stage is fed; difference means for generating an analogue difference signal representing the difference between the signal held by the sample and hold stage and the output from the digital to analogue conversion stage; a second analogue to digital conversion stage for generating a digital output corresponding to the difference signal; and combining means for combining the digital outputs of the first and second conversion stages to generate a digital output representing the sampled analogue inp

REFERENCES:
patent: 3597761 (1971-08-01), Fraschilla et al.
patent: 3721975 (1973-03-01), Brinkman et al.
patent: 4058806 (1977-11-01), Nadler
patent: 4897656 (1990-01-01), Van de Plassche et al.
patent: 4912469 (1990-03-01), Van de Grift et al.
patent: 5072220 (1991-12-01), Petschacher et al.
patent: 5151700 (1992-09-01), Matsuzawa et al.

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