Sub-ranging analog-to-digital converter

Details Sub-ranging analog-to-digital converter Sub-ranging analog-to-digital converter

1993-10-21

1995-10-17

Young, Brian K.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

H03M 120

Patent

active

054594650

ABSTRACT:
The present invention provides a sub-ranging analog-to-digital (A/D) converter with improved speed and power consumption characteristics relative to known sub-ranging converters. The sub-ranging A/D converter utilizes information relating to the values of the bits determined in one stage to define the range of operation for a subsequent stage. In one embodiment, the subsequent stage utilizes three-input comparators in determining the value of a bit. Two of the inputs are used to receive signals representative of the upper and lower limits of the range of operation that has been determined by the prior stage and the other input is used to receive the analog signal. The three-input comparator operates to produce an output signal that is indicative of the relationship of the analog signal to a threshold level within the defined range of operation determined by the prior stage.

REFERENCES:
patent: 4409497 (1983-10-01), Nagano
patent: 4528591 (1985-07-01), Liepe et al.
patent: 4827191 (1989-05-01), Chapman
patent: 4928103 (1990-05-01), Lane
patent: 4978957 (1990-12-01), Hotta et al.
Kazunori Tsugaru, Yasuhiro Sugimoto, Makoto Noda, Hiroshi Iwai, Gen Sasaki and Yoshito Suwa, "A 10BIT 40MHz ADC Using 0.8um BI-CMOS Technology," pp. 48-51 IEEE, 1989 (place of publication not indicated).

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