Sub-problem extraction method for wiring localized congestion ar

Details Sub-problem extraction method for wiring localized congestion ar Sub-problem extraction method for wiring localized congestion ar

1996-03-21

1997-09-30

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, G06F 1750

Patent

active

056732015

ABSTRACT:
A computer-implementable method for wiring congested areas in a VLSI design detects overflows indicating an area of congestion in the VLSI design and defines a bounding area around the area of congestion. Attachment points are created at locations where wires cross the bounding area and the entire bounding area, with the attachment points, is extracted from the VLSI design as a sub-design. Initial wire weights are assigned to wiring parameters associated with the sub-design. Thereafter, an iterative process is commenced to derive a wiring solution for the sub-design. In a first step of the iterative process, an attempt is made to wire the sub-design with the assigned wire weights. In subsequent steps, at least one wire weight is changed and a new attempt is made to wire the sub-design using the new wire weight values. The process continues in this manner until a wiring attempt completes successfully. The wired solution for the sub-design is then placed back into the VLSI design.

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