Sub-picosecond multiphase clock generator

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S161000, C327S244000, C327S245000

Reexamination Certificate

active

11951217

ABSTRACT:
A circuit apparatus and method for generating multiphase clocks in a delay lock loop (DLL) at sub-picosecond granularity. The circuit and method of the invention involves locking a number of cycles M in an N stage DLL, e.g., M cycles, where M is an prime number, which results in clock edges in each cycle that are not located at the same phase locations in each of the M cycles. Any of the phase locations from any of the cycles can be used to generate a clock edge for all cycle in the system application. This requires a special technique to “lock” the DLL loop over a M cycle period instead of a one cycle period. The benefit is that it improves the clock placement granularity by a factor of M over the previous art.

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