Sub-nanosecond calibrated delay line structure

Details Sub-nanosecond calibrated delay line structure Sub-nanosecond calibrated delay line structure

1993-09-10

1995-05-30

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327271, 327272, 327276, 327278, 327281, 327284, 327285, 327288, H03H 1126

Patent

active

054205310

ABSTRACT:
Disclosed is a digital phase-locked loop circuit which provides a control signal (332, 334) for a delay circuit (304, 306, 308, 310) within the feedback path of the phase-locked loop. The circuit has a first series of delay circuits (304, 306, 308, 310), which have an incremental control signal input (332, 334), to delay an input clock signal (302) to provide the D input (311) to a D flip flop (312). The input clock signal (302) is also connected to a second series of delay circuits (314, 316, 318, 320, 322). The output of this second series (314, 316, 318, 320, 322) is connected to the clock input (323) of the D flip flop (312). The voltage controlled delay signal input for the second series of delay circuits (314, 316, 318, 320, 322) is supplied by a reference control signal (124, 126). The output of the D flip flop (312) is passed through a resistor-capacitor filtering circuit (324, 325) and fed back to the first series of delay circuits (304, 306, 308, 310) as the incremental control signal. The delay through the first series of circuits is incrementally larger than the delay through the second, reference, series of delay circuits.

REFERENCES:
patent: 5101117 (1992-03-01), Johnson et al.
patent: 5216302 (1993-06-01), Tanizawa

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