Sub-nanosecond calibrated delay line structure

Details Sub-nanosecond calibrated delay line structure Sub-nanosecond calibrated delay line structure

1991-02-07

1993-03-09

Howell, Janice A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307597, 307602, 307603, 307605, 307606, 328 55, 328 66, H03K 5159, H03K 301

Patent

active

051928868

ABSTRACT:
Disclosed is a digital phase-locked loop circuit which provides a control signal for a delay circuit within the feedback path of the phase-locked loop. The circuit has a first series of delay circuits, which have an incremental control signal input, to delay an input clock signal to provide the D input to a D flip flop. The input clock signal is also connected to a second series of delay circuits. The output of this second series is connected to the clock input of the D flip flop. The voltage controlled delay signal input for the second series of delay circuits is supplied by a reference control signal. The output of the D flip flop is passed through a resistor-capacitor filtering circuit and fed back to the first series of delay circuits as the incremental control signal. The delay through the first series of circuits is incrementally larger than the delay through the second, reference, series of delay circuits.

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patent: 5054038 (1991-10-01), Hedberg
T. Otsuji and N. Narumi, "A 10-ps Resolution Process-Insensitive Timing Generator IC", IEEE Journal of Solid State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1412-1418.

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