Sub-nanoscale electronic devices and processes

Details Sub-nanoscale electronic devices and processes Sub-nanoscale electronic devices and processes

1996-02-01

2001-11-20

Geist, Gary (Department: 1623)

Active solid-state devices (e.g., transistors, solid-state diode

Organic semiconductor material

C257S487000, C438S049000, C438S957000

Reexamination Certificate

active

06320200

ABSTRACT:

PARTIAL WAIVER OF COPYRIGHT
All of the material in this patent application is subject to copyright protection under the copyright laws of the United States and of other countries. As of the first effective filing date of the present application, this material is protected as unpublished material.
Portions of the material in the specification and drawings of this patent application are also subject to protection under the maskwork registration laws of the United States and of other countries.
However, permission to copy this material is hereby granted to the extent that the owner of the copyright and maskwork rights has no objection to the facsimile reproduction by anyone of the patent document or patent disclosure, as it appears in the United States Patent and Trademark Office patent file or records, but otherwise reserves all copyright and maskwork rights whatsoever.
BACKGROUND AND SUMMARY OF THE INVENTION
The present inventions relate to a new generation of electronic microcircuit technology, having dimensions much smaller than those of semiconductor integrated circuits, and to related systems and processes.
To better explain the significance and advantages of these innovations, the following paragraphs will review some technological context. This technological context is not necessarily prior art, but is intended to help in pointing out the disclosed inventions.
The Era of Downscaling
Since about 1960, the steady downscaling of integrated circuit minimum dimensions has permitted ever-increasing density, and thus an ever-increasing range of functionality at an ever-more favorable cost. This wealth of opportunity has permitted system designers to introduce many of the electronic products which have revolutionized industry and daily life in these decades. Continued downscaling steadily improves the available functionalities and pricing, and thus steadily challenges system designers. This fosters a continuing climate of active innovation and competition.
The most obvious index of downscaling is the steady reduction in the “minimum geometry” which can be specified for fabrication of an integrated circuit. This corresponds to a reduction in the size and spacing of the individual transistors, and thus steadily increases the number of transistors which can be fabricated in a given area. However, it is important to note that scaling has also provided exponential improvements in device speed and power dissipation, which has led to substantial enhancement of system performance. Thus, an end to the epoch of downscaling would drastically reduce the speed of progress in electronics.
Limitations of Semiconductor Microelectronics
The danger now in sight is that the downscaling of minimum geometries of transistor-based integrated circuits will eventually be brought to an end by a combination of problems related to devices, interconnections, noise, and reliability.
1
The resulting saturation of circuit densities almost certainly implies a saturation of the historical exponentially downward trend in cost and volume per bit or function.
1
These issues have been widely discussed; see, e.g., Chatterjee et al., 130, P
ROC
. IEE 105 (1983), which is hereby incorporated by reference.
A technology-dependent issue is where existing ULSI (“ultra-large-scale integration,” i.e. semiconductor fabrication with minimum dimensions of a micron or less) will usefully end. From recent work, it is reasonable that this will occur in the 0.1 micron regime; scaling to just the 100s of Å level may not be cost-effective in relation to the development costs of the technology. Thus, identifying an atomic-scale device technology seems the only approach worth the investment.
Several constraints are visibly converging to cut off the advantages of further scaling. While it is likely that clever process modifications can postpone the impact of some constraints, it does not seem likely that all can be avoided.
Alignment Tolerances
One of the basic problems is alignment tolerances: formation of features at a small minimum size &lgr; does not imply that that minimum size can be used for fabrication of working circuits: it is also necessary to have alignment tolerances which are much smaller than &lgr; (preferably well under &lgr;/4). (Thus, a 0.8&mgr; lithography process will typically have a specified alignment tolerance of ±0.15&mgr; or less.)
With further scaling, this imposes several nonobvious difficulties. One is thermal stability, as discussed below.
Dopant Diffusion Lengths
Diffusion lengths scale approximately as (Dt)
½
, where t is time at the highest temperature, and D is a temperature-dependent diffusion constant characteristic of the dopant and the background material. As dimensions are reduced, the dopant diffusion lengths in silicon are posing difficulties in process design. In the past decade, many accommodations have been made to reduce dopant mobility and to reduce time at high temperatures. However, it is not clear that such accommodations can be continued indefinitely. For example, arsenic (or antimony) dopants are now used increasingly in place of phosphorus, but there is no suitale N-type dopant with significantly lower diffusivity than these two.
Punch-through, Doping Levels, Electric Fields, and Hot Electrons
A voltage applied across a semiconductor junction (in the reverse-bias direction) will naturally create a depletion region around the junction. The width of the depletion region depends on the doping levels of the semiconductor. If the depletion region spreads to contact another depletion region, “punch-through,” i.e. uncontrolled current flow, may occur.
Higher doping levels will help to minimize the separations required to prevent punch-through. However, if the voltage change per unit distance is large, this creates a further difficulty.
A large voltage change per unit distance implies that the magnitude of the electric field is large. An electron traversing such a sharp gradient may be accelerated to an energy level significantly higher than the minimum conduction band energy. Such an electron is known as a “hot” electron, and may be sufficiently energetic to pass through an insulator. Thus, hot electrons can irreversibly degrade some common types of devices.
Isolation in a Monolithic Semiconductor Substrate
Conventional semiconductor integrated circuit technology uses a monolithic substrate which is all one crystal. Such substrates provide great advantages in processing. However, this device architecture poses some inherent difficulty with further scaling. One difficulty is lateral isolation of devices from each other. Another difficulty is leakage current scaling. Another difficulty is presented by the diffusivity of carriers within the substrate: free carriers (generated, e.g., by an alpha particle hit) can diffuse over many tens of microns to help neutralize a stored charge. Some attempts have been made to overcome these difficulties by using total isolation from the substrate, but to date such technologies have not demonstrated favorable economics of scaling.
Considerations in Further Downscaling
Theoretically, further downscaling of devices would still be achievable with the appropriate device technology, IF the approach could simultaneously address the interconnection, reliability, and implied fabrication limitations. Estimates based on abstract physical switching device models which are independent of specific device technologies indicate that several orders of magnitude in downscaling of device power in devices would be theoretically permitted,
2
if an appropriate device technology could be found. The key to this search is to employ electronic phenomena which are characterized by dimensions much smaller than the depletion layer widths and diffusion lengths which provide the basis for conventional transistor function.
2
See R. T. Bate, “VLSI Electronics” (N. G. Einspruch, ed.), Vol. 5, p. 359 (Academic Press 1982), which is hereby incorporated by reference.
Limitations of Semiconductor Nanoelectronics
Within the last decade, tremendous progress in semiconductor

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