Sub-micron bonded SOI by trench planarization

Details Sub-micron bonded SOI by trench planarization Sub-micron bonded SOI by trench planarization

1993-08-18

1996-12-17

Carroll, J.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

437 61, 437 62, 437 63, 437225, 437235, 437974, H01L 2900

Patent

active

055856616

ABSTRACT:
A silicon on insulator substrate 8 provides islands of silicon 18 of uniform thickness by using a trench etch process and a silicon nitride layer 20 to provide a thickness control and polish stop for the silicon islands 18.

REFERENCES:
patent: 5091331 (1992-02-01), Delgado et al.
patent: 5162254 (1992-11-01), Usui et al.
patent: 5262346 (1993-11-01), Bindal et al.
patent: 5264395 (1993-11-01), Bindal et al.
patent: 5356513 (1994-10-01), Burke et al.
patent: 5399233 (1995-03-01), Murazumi et al.
Full English translation of Japan Kokai 1-13628 as per USPTO.
S. M. Sze, VLSI Technology, McGraw-Hill (1988) pp. 37-43.
E. Bassous, "Fabrication of Novel Three-Dimensional Microstructures by the Anisotropic Etching of (100) and (110) Silicon", IEEE Transactions on Electron Devices, vol. ED-25, No. 10, (Oct. 1978).

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