Sub-layer contact technique using in situ doped amorphous silico

Details Sub-layer contact technique using in situ doped amorphous silico Sub-layer contact technique using in situ doped amorphous silico

1991-04-29

1993-03-09

Chadhuri, Olik

Fishing, trapping, and vermin destroying

437101, 437203, 437233, 437247, 437967, 148DIG50, H01L 2120

Patent

active

051927080

ABSTRACT:
A method of providing sublayer contacts in vertical walled trenches is proposed. In accordance with the present invention, the phosphorus doped amorphous silicon is deposited at temperatures less than 570.degree. C. The conversion into the extremely large crystal low resistivity polysilicon is accomplished by a low temperature anneal at 400.degree. C. to 500.degree. C. for several hours and a short rapid thermal anneal (RTA) treatment at a high temperature approximately 850.degree. C. for twenty seconds. These two conversion heat treatments are done at sufficiently low thermal budget to prevent any significant dopant movement within a shallow junction transistor. After anneal, the excess low resistivity silicon is planarized away by known techniques such as chemical/mechanical polishing. In addition, due to the trench filling abilities of the amorphous silicon CVD process, in one preferred embodiment of the invention the capability of accessing subsurface silcon layers at different trench depths is demonstrated.

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