Sub-CPU monitoring system including dual port memory

Details Sub-CPU monitoring system including dual port memory Sub-CPU monitoring system including dual port memory

1995-02-02

1996-06-04

Beausoliel, Jr., Robert W.

C06F 1300

Patent

active

055242065

ABSTRACT:
A multiprocessor system including dual port memories (DPMs), each DPM used as a shared memory circuit for a host CPU circuit and one of sub CPU circuits. Each sub CPU writes an operation information thereof in a monitor information memory portion of an associated DPM after data write to a data portion of the DPM every data collection. The host CPU references the operation information in the monitor information memory portion and reads data from the DPM after a normal operation of the sub CPU is confirmed. When the sub CPU operates abnormally, the host CPU resets the sub CPU operating normally. A watch-dog timer monitors only operation of the host CPU.

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