Stud bumps for die alignment

Details Stud bumps for die alignment Stud bumps for die alignment

2011-02-01

2011-02-01

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S737000, C257SE23031, C438S123000

Reexamination Certificate

active

07880287

ABSTRACT:
Embodiments include but are not limited to apparatuses and systems including a package having stud bumps for die alignment. A package may include a package substrate, and a plurality of stud bumps coupled to the package substrate. The stud bumps may define a die region of the package substrate in which movement of a die disposed within the die region is restricted prior to attachment of the die to the package substrate, wherein the plurality of stud bumps comprise a profile that is less than a profile of the die when attached to the package substrate. Other embodiments may be described.

REFERENCES:
patent: 5453701 (1995-09-01), Jensen et al.
patent: 5895554 (1999-04-01), Gordon
patent: 6980014 (2005-12-01), Akram et al.
patent: 7407085 (2008-08-01), Susheel

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