STS frame-ATM cell circuit emulation apparatus and frame...

Details STS frame-ATM cell circuit emulation apparatus and frame... STS frame-ATM cell circuit emulation apparatus and frame...

2011-03-08

2011-03-08

Ly, Anh-Vu (Department: 2472)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

Reexamination Certificate

active

07903668

ABSTRACT:
A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.

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Co-pending U.S. Appl. No. 11/240,626, filed Oct. 3, 2005; Souichi Kataoka et al., entitled “STS Frame-ATM Cell Circuit Emulation Apparatus and Frame Length Compensation Method for the Same”.

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