Structures for improving heat dissipation in stacked...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip

Reexamination Certificate

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C257S787000

Reexamination Certificate

active

06737750

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to a semiconductor package and a method for fabricating a semiconductor package.
2. Related Art
Semiconductor packages that include stacked semiconductor dies (otherwise known as semiconductor “chips” or “integrated circuits”) are becoming increasingly popular. Such packages allow dies that perform the same function (e.g., two memory dies) or different functions (e.g., a processor die and a memory die) to be combined into a single package. This improves density and is especially useful in applications where package size is important, such as in cell phones, PDAs, camcorders, and other wireless consumer products.
Conventional stacked semiconductor packages typically include a substrate, such as a leadframe, tape, or laminate substrate, upon which a pair of dies are mounted. A bottom die is attached by an adhesive layer to a mounting area on a surface of the substrate. A top die is attached to the bottom die with an adhesive layer.
One disadvantage of stacked semiconductor packages is that it is difficult to effectively dissipate the heat generated by the top and bottom dies. For example, heat generated by the top die flows from the top die through the adhesive layer into the bottom die. This raises the temperature of the bottom die and thus can degrade the performance of the bottom die.
What is needed is a semiconductor package for plural dies with improved thermal
SUMMARY
In one embodiment of the present invention, a semiconductor package is provided. The semiconductor package includes a substrate having a first surface. A first die is mounted on the first surface of the substrate. A free-standing, rigid support structure having at least one aperture formed therein is disposed over the first die on the first surface of substrate. A second die is mounted on the support structure. An encapsulant fills within the support structure and covers the first die, the support structure, and the second die. Both the first and second dies are electrically connected to circuit patterns on the first surface of the substrate. The support structure may be thermally coupled to the substrate, thereby providing heat transfer from the second die, and also may be electrically coupled to a circuit pattern of the first surface of the substrate, thereby providing a voltage to the inactive backside of the second die and/or a voltage input to the second die.
In another embodiment of the present invention, a semiconductor package includes a substrate having a first surface. A first die is in a flip chip connection with a plurality of circuit patterns on the first surface of the substrate. A thermally conductive first heat spreader having a first surface and an opposite second surface is disposed over the first die and is thermally coupled between the inactive backside of the first die and the substrate. The inactive backside of a second die is mounted on and is thermally coupled to the first heat spreader over the first die. The second die may be electrically connected to circuit patterns of the first surface of the substrate by wires that extend through openings in the heat spreader. A second heat spreader may be provided over the second die and the first heat spreader, and may be thermally coupled between the second die and either the substrate or the first heat spreader.


REFERENCES:
patent: 4763188 (1988-08-01), Johnson
patent: 5012323 (1991-04-01), Farnworth
patent: 5025306 (1991-06-01), Johnson et al.
patent: 5166772 (1992-11-01), Soldner et al.
patent: 5200809 (1993-04-01), Kwon
patent: 5291061 (1994-03-01), Ball
patent: 5323060 (1994-06-01), Fogal et al.
patent: 5347429 (1994-09-01), Kohno et al.
patent: 5365107 (1994-11-01), Kuraishi et al.
patent: 5422435 (1995-06-01), Takiar et al.
patent: 5463253 (1995-10-01), Waki et al.
patent: 5495398 (1996-02-01), Takiar et al.
patent: 5502289 (1996-03-01), Takiar et al.
patent: 5530202 (1996-06-01), Dais et al.
patent: 5656864 (1997-08-01), Mitsue et al.
patent: 5689135 (1997-11-01), Ball
patent: 5696031 (1997-12-01), Wark
patent: 5715147 (1998-02-01), Nagano
patent: 5721452 (1998-02-01), Fogal et al.
patent: 5739581 (1998-04-01), Chillara et al.
patent: 5793108 (1998-08-01), Nakahishi et al.
patent: 5815372 (1998-09-01), Gallas
patent: 5866949 (1999-02-01), Schueller
patent: 5886412 (1999-03-01), Fogal et al.
patent: 5973403 (1999-10-01), Wark
patent: 6005778 (1999-12-01), Spielberger et al.
patent: RE36613 (2000-03-01), Ball
patent: 6051886 (2000-04-01), Fogal et al.
patent: 6057598 (2000-05-01), Payne et al.
patent: 6072243 (2000-06-01), Nakanishi
patent: 6080264 (2000-06-01), Ball
patent: 6133637 (2000-10-01), Hikita et al.
patent: 6214641 (2001-04-01), Akram
patent: 6246115 (2001-06-01), Tang et al.
patent: 6326696 (2001-12-01), Horton et al.
patent: 6429512 (2002-08-01), Huang et al.
patent: 503 201 (1991-12-01), None
patent: 56062351 (1981-05-01), None
patent: 60182731 (1985-09-01), None
patent: 61117858 (1986-06-01), None
patent: 62126661 (1987-06-01), None
patent: 63128736 (1988-06-01), None
patent: 63-244654 (1988-10-01), None
patent: 1028856 (1989-01-01), None
patent: 64001269 (1989-01-01), None
patent: 1071162 (1989-03-01), None
patent: 1099248 (1989-04-01), None
patent: 3169062 (1991-07-01), None
patent: 4028260 (1992-01-01), None
patent: 4-56262 (1992-02-01), None
patent: 4056262 (1992-02-01), None
patent: 4096358 (1992-03-01), None
patent: 4116859 (1992-04-01), None
patent: 5013665 (1993-01-01), None
patent: 5-75015 (1993-03-01), None
patent: 5109975 (1993-04-01), None
patent: 5136323 (1993-06-01), None
patent: 10-256470 (1998-09-01), None

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