Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is
Reexamination Certificate
2000-04-26
2001-10-30
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
C257S301000, C257S304000
Reexamination Certificate
active
06310359
ABSTRACT:
BACKGROUND OF THE INVENTION
In construction of microelectronic devices, it is well known that there is a constant pressure for reduction of device size and/or increase of device capability at a given scale.
In the actual construction of reduced scale devices, attention must be paid to higher precision in configuring the materials from which the device components are formed. Attention must also be paid to the interaction of the various materials used in device construction during the device manufacture process, during device testing, and during device operation. In this regard, finer sized device components are more sensitive to adverse materials interactions since the amount of material forming the component is smaller. For example, an interaction that might have only affected the border area of a large component would affect an entire component of smaller scale (e.g., where the scale of the smaller component is the same size as the border area of the larger component). Thus, reduction in component scale forces consideration of materials interaction problems which could have been viewed as non-critical for larger scale components.
In the context of devices such as deep trench capacitors in semiconductor substrates, the various materials used to form the components of the capacitor such as the capacitor plates (electrodes), the dielectric barrier between electrodes, oxide collar structures to prevent or minimize parasitic effects, surface or buried straps to provide contact between the capacitor and the other circuitry of the device, etc. For example, the electrode in the trench is typically a highly doped polycrystalline silicon (polysilicon) material, the buried or surface strap is typically an amorphous silicon, and the semiconductor substrate is a monocrystalline silicon. The successful functioning of the capacitor depends in part on the ability of these diverse materials to maintain their original or desirably modified character during manufacture/useful life of the device.
Unfortunately, the nature of these materials is such that unwanted interactions may occur unless otherwise prevented.
For example, a problem may be caused by the difference in crystallinity (or grain size) between the monocrystalline silicon substrate and the amorphous or polycrystalline silicon trench electrode material, especially where there is an intervening amorphous silicon material. In such configurations, the amorphous or polysilicon layer may template on the monocrystalline surface and recrystallize. Often, defects are created at the interface with the monocrystalline silicon during recrystallization which may propagate into the monocrystalline silicon. The occurrence of such defects is believed to adversely affect memory cell performance (the memory cell containing the capacitor). Specifically, the defects are believed to cause a lack of predictability of the charge retention time for the capacitor (so-called variable retention time). Such lack of predictability may limit the usefulness of the resulting device and/or the ability to maximize design performance.
U.S. patent application Ser. No. 09/213,674, filed Dec. 17, 1998, discloses use of quantum conductive barriers in trench capacitors to address variable retention time problems. Nevertheless, there is a need for quantum conductive barrier materials and structures that provide improved trench capacitor performance, especially reduced single cell fails and low temperature fails. There is also a need for improved quantum conductive barrier materials which provide improved control over dopant atoms commonly present in semiconductor electronic devices.
SUMMARY OF THE INVENTION
The invention provides novel and improved quantum barrier layer structures and compositions which enable reduced scale capacitor structures of improved reliability and other device structures where the quantum conductive barrier function is desired. The invention also provides improved materials configurations which enable improved performance of existing quantum conductive barrier technology.
In one aspect, the invention encompasses quantum conductive barrier layer structures comprising a quantum conductive barrier layer with an adjacent layer of amorphous, microcrystalline semiconductor material or partially crystalline semiconductor material. Alternatively, the invention encompasses quantum conductive barrier layer structures comprising a plurality of quantum conductive barrier layers with thin layers of amorphous, microcrystalline or partially crystalline semiconductor material therebetween.
In another aspect, the invention encompasses improved quantum conductive barrier layer compositions comprising Si—O—N materials having improved dopant ion diffusion characteristics enabling control (in combination with the thermal history of the subject device) of dopant concentration and depth profile.
In another aspect, the invention encompasses deep trench capacitors comprising a quantum conductive barrier structure of the invention.
In another aspect, the invention encompasses device structures using quantum conductive barrier structures of the invention.
The invention also encompasses methods for making the above structures and devices.
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Aussilhou Caroline
Buchet Corinne
Chaloux Susan E.
Greer Heidi L.
Jammy Rajarao
Capella Steven
International Business Machines - Corporation
Le Dung A
Nelms David
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