Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2011-06-07
2011-06-07
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180, C365S185220, C365S185240
Reexamination Certificate
active
07957188
ABSTRACT:
A method of trimming FET NVM cells in Multi-Level-Cell (MLC) operation is provided. The method comprises (a) applying a first voltage and a second voltage to a control gate and a bulk of the over-programmed FET NVM cell, respectively; and (b) applying a signal to a drain of the over-programmed FET NVM cell for a time period to produce a limited threshold voltage reduction; wherein polarities of the first voltage and the second voltage are opposite to that of the signal. Thus, the charge placement in the storing material could be precisely controlled within a small range of charge state and produce a multi-bits/cell of higher digital storage density.
REFERENCES:
patent: 5142496 (1992-08-01), Van Buskirk
patent: 5771346 (1998-06-01), Norman et al.
patent: 5991203 (1999-11-01), Choi
patent: 6212103 (2001-04-01), Ahrens et al.
Huang Jui-Hung
Wang Lee Z.
FS Semiconductor Corp., Ltd.
Muncy Geissler Olds & Lowe, PLLC
Nguyen Tan T.
LandOfFree
Structures and methods of trimming threshold voltage of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Structures and methods of trimming threshold voltage of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Structures and methods of trimming threshold voltage of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2713644