Structures and methods for enhancing erase uniformity in a...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185180

Reexamination Certificate

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11695668

ABSTRACT:
A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are connected to a common node for enhancing the erase uniformity of the nitride read-only memory array. If an operation requests erasing on the left side of nitride read-only memory cells, a positive voltage is supplied from an internal power supply to the left side for each of the nitride read-only memory cells, and the right side for each of the nitride read-only memory cells is discharged to a common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.

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patent: 6577540 (2003-06-01), Choi
patent: 6795348 (2004-09-01), Mihnea et al.
patent: 6891760 (2005-05-01), Ohtani

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