Structure to reduce line-line capacitance with low K material

Details Structure to reduce line-line capacitance with low K material Structure to reduce line-line capacitance with low K material

2001-12-31

2003-07-29

Cuneo, Kamand (Department: 2829)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S499000, C257S506000

Reexamination Certificate

active

06600207

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an improved method and process flow for integrated circuit manufacture and more particularly, to a method and process flow for reducing line to line capacitance in integrated circuit devices by using low dielectric constant materials.
BACKGROUND OF THE INVENTION
As advances in processing technology allow for an increasing number of devices to be fabricated on a single integrated circuit (IC), the surface area or size of each individual device on the IC is scaled down or reduced. Conductive lines or interconnects that electrically couple such individual devices, are also scaled. However, the same scaling factor applied to line width and line to line spacing is not generally applied to interconnect line thickness due to the need to maintain minimum current carrying capacity. Thus, interconnect lines are often thicker than that which the scaling factor employed for the line width would predict.
Adjacent interconnect lines form a capacitor where the plate area of each plate of the capacitor formed is the product of the length of the line and its thickness, over that length. The capacitance of such a capacitor is directly proportional to area of the capacitor plates and the dielectric constant of the dielectric material disposed between the plates, and inversely proportional to the distance between the capacitor plates (line—line spacing). Thus, as IC's are scaled down in size the line to line spacing decrease and the increased number of lines that are needed to interconnect the increased number of devices, results in an increase in the line to line capacitance. In addition to this line to line capacitance, the capacitance between interconnects of adjacent levels, often referred to as cross-talk is also a factor in an IC's total interconnect capacitance. In some high speed circuits, this interconnect capacitance can be the limiting factor in the speed at which the IC can function. Thus it would be desirable to be able to reduce this total interconnect capacitance.
A significant factor in the value of interconnect capacitance is the dielectric constant of the materials that surround interconnect lines, as capacitance is directly proportional to such material's dielectric constant. For example, where silicon nitride, with a dielectric constant of about 7.0, is used as such a material, the resulting capacitance is higher than if silicon dioxide, with a dielectric constant of about 3.9, were employed. However, as silicon oxide is currently the most commonly used material, reduced interconnect capacitance is dependent on new, lower dielectric constant materials. However, it has been found that use of such low dielectric constant (low-K) materials is often problematic.
Thus it would be advantageous to provide improved methods for fabricating advanced IC's that reduce or eliminate this increase in interconnect capacitance as IC's are scaled down in size. It would be desirable if these improved methods provided for forming interconnect lines with low line to line capacitance within a layer of interconnect lines. In addition, it would be desirable if the methods also served to reduce cross-talk between interconnect lines of adjacent layers of such lines. It would also be desirable if this processing method and flow was readily integratable into a standard semiconductor process flow, thus avoiding increased costs and yield losses due to increased process complexity. In this manner, smaller, faster, more complex, and more densely packed integrated circuits such as DRAMs and the like are provided.
SUMMARY
Methods for forming an integrated circuit having an interconnect structure that employs low dielectric constant materials are provided. Such methods provide for a lower total interconnect capacitance than methods that employ standard dielectric materials with dielectric constants equal to or greater than that of silicon dioxide.
In some embodiments in accordance with the present invention, dielectric regions are formed that encompass a low dielectric constant material and another dielectric material having a higher dielectric constant. Such regions are employed to define regions where interconnects are to be formed. In some embodiments of the present invention, such low dielectric constant interconnect structures are formed for a single interconnect layer, while in other embodiments, such low dielectric constant interconnect structures are formed for multiple interconnect layers within the integrated circuit. In some embodiments of the present invention, the dielectric regions are converted into low dielectric constant regions, also referred to as low-K regions, where one or more low dielectric constant materials are employed for forming the low-K region structure, the one or more low dielectric constant materials having different insulative properties.
Some embodiments in accordance with the present invention employ a copper or copper alloy metallization for such interconnects while other embodiments employ aluminum or an aluminum alloy metallization for such interconnects. In some embodiments, the low dielectric material is formed using a liquidus precursor material in a spin-on coating process, while in other embodiments, a chemical vapor deposition (CVD) process is employed to form the low dielectric constant material. In some embodiments of the present invention, a barrier layer is formed overlying a layer of low dielectric constant material prior to forming another layer of dielectric material, in other embodiments, such a barrier layer is not employed. Where a barrier layer is formed, some such layer can also serve as an etch-stop layer for etching another dielectric constant material from the low dielectric constant material.
Some embodiments in accordance with the present invention employ at least one refractory metal nitride barrier layer to isolate the interconnect lines from the dielectric material. In some embodiments such a refractory metal barrier layer is conductive, in other embodiments it is not conductive.
In some embodiments of the present invention, multiple levels of interconnects are formed having multiple low-K region structures formed of one or more low-K materials, where the one or more materials can have different insulative properties. In some multiple level embodiments in accordance with the present invention, a single type low-K material is employed for each low-K region, while in some embodiments more than one low-K material and or standard dielectric constant material is employed to form a dielectric region having a dielectric constant less than that which would be obtained if only such standard materials are employed.


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