Structure of stacked integrated circuits

Details Structure of stacked integrated circuits Structure of stacked integrated circuits

2001-01-23

2002-08-27

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S686000, C257S723000, C257S783000

Reexamination Certificate

active

06441496

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a structure of stacked integrated circuits and method for manufacturing the same, in particular, to a structure of stacked integrated circuits in which integrated circuits can be effectively stacked so as to facilitate the manufacturing processes.
2. Description of the Related Art
In the current technological field, every product needs to be light, thin, and small. Therefore, it is preferable that the integrated circuit has a small volume in order to meet the demands of the products. In the prior art, even if the volumes of integrated circuits are small, they only can be electrically connected to the circuit board in parallel. Because the area of the circuit board is limited, it is not possible to increase the number of the integrated circuits mounted on the circuit board. Therefore, it is difficult to make the products small, thin, and light.
To meet the demands of manufacturing small, thin, and light products, a lot of integrated circuits can Se stacked. However, when stacking a lot of integrated circuits. the upper integrated circuit will contact and press the wirings of the lower integrated circuit. In this case, the signal transmission to or from the lower integrated circuit is easily influenced.
Referring to
FIG. 1
, a structure of stacked integrated circuits includes a substrate
10
, a lower integrated circuit
12
, an upper integrated circuit
14
, a plurality of wirings
16
and
17
, and an isolation layer
18
. The lower integrated circuit
12
is located on the substrate
10
. The isolation layer
18
is located on the lower integrated circuit
12
. The upper integrated circuit
14
is stacked on the isolation layer
18
. That is, the upper integrated circuit
14
is stacked above the lower integrated circuit
12
with the isolation layer
18
interposed between the integrated circuits
12
and
14
. Thus, a proper gap
20
is formed between the lower integrated circuit
12
and the upper integrated circuit
14
. According to this structure, the plurality of wirings
17
can be electrically connected to the edge of the lower integrated circuit
12
. Furthermore, the plurality of wirings
17
connecting the substrate
10
to the lower integrated circuit
12
are free from being pressed when stacking the upper integrated circuit
14
above the lower integrated circuit
12
.
However, the above-mentioned structure has the disadvantages described hereinbelow. During the manufacturing processes, the isolation layer
18
has to be manufactured in advance, and then, it is adhered to the lower integrated circuit
12
. Thereafter, the upper integrated circuit
14
has to be adhered on the isolation layer
18
. As a result, the manufacturing processes are complicated, and the manufacturing costs are high.
To solve the above-mentioned problems, it is necessary for the invention to provide a structure of stacked integrated circuits in order to improve the stacking processes of the integrated circuits, facilitate the manufacturing processes. and lower down the manufacturing costs.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a structure of stacked integrated circuits and method for manufacturing the same in order to effectively stack the integrated circuits and increase the manufacturing speed.
It is therefore another object of the invention to provide a structure of stacked integrated circuits and method for manufacturing the same in which the stacking processes can be simplified because an isolation layer can be simultaneously formed on the integrated circuit when coating the adhesive layer.
It is therefore still another object of the invention to provide a structure of stacked integrated circuits and method for manufacturing the same in which the adhesive layer and isolation layer can be formed simultaneously by a general coater. Thus, no other apparatus should be prepared for manufacturing the stacked integrated circuits.
According to one aspect of the invention, a structure of stacked integrated circuits includes a substrate, a lower integrated circuit, a plurality of wirings, an adhesive layer, and an upper integrated circuit. The substrate has a first surface formed with signal input terminals, and a second surface formed with signal output terminals. The lower integrated circuit has a first surface and a second surface. The first surface of the lower integrated circuit is adhered to the first surface of the substrate while the second surface of the lower integrated circuit is formed with a plurality of bonding pads. The wirings have first ends and second ends. The first ends are electrically connected to the bonding pads of the lower integrated circuit while the second ends are electrically connected to the signal input terminals of the substrate. The adhesive layer is coated on the second surface of the lower integrated circuit and includes adhesive agent and filling elements. The upper integrated circuit is stacked above the second surface of the lower integrated circuit with the adhesive layer inserted between the upper and lower integrated circuits. The lower integrated circuit is adhered to the upper integrated circuit by the adhesive agent. A predetermined gap is formed between the lower and upper integrated circuits by the filling elements.
According to this structure, the lower integrated circuit is free from being pressed and damaged by the upper integrated circuit when stacking a plurality of integrated circuits. Thus, the stacking processes can be facilitated and the manufacturing costs can also be lowered.


REFERENCES:
patent: 6097097 (2000-01-01), Hirose
patent: 6333562 (2001-12-01), Lin

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