Structure of disturbing plate having down set

Details Structure of disturbing plate having down set Structure of disturbing plate having down set

2000-09-29

2002-07-02

Talbott, David L. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S667000, C257S787000, C257S670000, C257S673000, C257S674000

Reexamination Certificate

active

06414379

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a disturbing plate having at least one down set. More specifically, the present invention relates to a structure of a disturbing plate useful for the lead frame type package in the semiconductor device.
2. Description of the Related Art
In the ever-expanding world of information, the integrated circuit is an inseparable part of daily life. Food, clothing, residence, business, education, and amusement are just some of the areas which often use products made with integrated circuits. Following instant development, greater user-friendliness, increased usefulness and higher complexity in electronic products, as well as a trend towards lightness and smallness in design, use of electronic products has become more convenient and comfortable.
In the semiconductor fabricating process, a semiconductor product having higher integration is available because of mass production of the 0.18 micrometer integrated circuit. The integrated circuit fabrication process includes three major stages: production of a silicon chip, production of an integrated circuit and packaging of the integrated circuit, after which packaging the manufacture of the integrated circuit is complete. It is the object of the package to provide a medium for electrically connecting a die to a printed circuit board or other suitable components and to provide protection for the die.
After the process of fabricating a semiconductor is completed, the wafer is cut into dies. A bonding pad is usually provided in the periphery of the die as a testing point for detection of the die and a terminal for connection of the die to other components. A wire or a bump must be used as a connection medium to connect the die to other components.
Current methods of packaging a common semiconductor memory, such as a Dynamic Random Access Memory (DRAM), include Small Outline J-Lead (SOJ) and Thin Small Outline Package (TSOP).
It is noted that an SOJ or a TSOP includes a Lead On Chip (LOC) or a Chip On Lead (COL) packaging manner in view of the location of the lead frame. The LOC is used mainly as a package for Dynamic Random Access Memory (DRAM), as provided by IBM in U.S. Pat. No. 4,862,245 (1998), and is superior for its high transmitting speed, good heat dissipation and compact size. The COL is a lead frame as disclosed in U.S. Pat. No. 4,989,068, for example.
FIG. 1
is a schematic cross-sectional view of a conventional small out-line package LOC. As exemplified by a conventional Lead On Chip (LOC), a die
108
is attached under leads
109
by a glue layer
110
. Then, the die
108
is encapsulated with mold compound having a top mold compound section
106
and a bottom mold compound section
102
to form a package. The top mold compound section
106
has a thickness
116
. The bottom mold compound section
102
has a thickness
114
. The ratio of the thickness
116
to the thickness
114
is about 1:3. Because the top section
106
and the bottom section
102
have different thicknesses and volumes, they exhibit different degrees of shrinkage during cooling, resulting in warpage of the whole package.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a structure of a disturbing plate having at least one down set to achieve equal volumes of the top and bottom sections of the mold compound such that equivalent shrinkage thereof is obtained when cooling occurs to prevent warpage of the packaging elements.
According to the above and other objects of the present invention, a disturbing plate structure having at least one down set applicable in a lead frame-type package in a semiconductor is provided. Such a structure comprises at least a lead frame, a die, a glue layer, a plurality of disturbing plates, a top mold compound, and a bottom mold compound. The lead frame has a plurality of leads under which the die is attached by the glue layer. Two disturbing plates are located on two sides of the die. A space is formed by bending a first bent portion and a second bent portion of the disturbing plate down. Finally, the lead frame is encapsulated with a mold compound.
According to one preferred embodiment of the present invention, in the structure of the disturbing plate having at least one down set, applicable in semiconductor leadframe packaging, the first bent portion and the second bent portion of the disturbing plate can be bent to adjust the size of the space, such that the top mold compound section has substantially the same volume as the bottom mold compound section. This equalizes the degree of shrinkage during cooling, thus avoiding warpage of the packaging element.


REFERENCES:
patent: 5530286 (1996-06-01), Murakami et al.
patent: 5932923 (1999-08-01), Kim et al.

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