Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Reexamination Certificate
2002-06-24
2003-12-23
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
Reexamination Certificate
active
06668035
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a delta-sigma fractional type divider, and more particularly to, a structure of a delta-sigma fractional type divider which is simple, has a wide-band frequency mixing capability and can obtain a delta-sigma mode by maximum.
2. Description of the Prior Art
A frequency synthesizer is a circuit for obtaining necessary frequencies depending on a digital code value. The frequency synthesizer is mainly divided into an integer type frequency synthesizer for producing an output frequency of an integer times using an input frequency of a frequency-phase detector, and a fractional type frequency synthesizer improved in phase, synchronizing time, etc. compared to the integer type frequency synthesizer.
The fractional type frequency synthesizer has a high spur in process of being implemented even though it's various advantages. Thus, the fractional type frequency synthesizer has a current compensation structure using digital-analog converter, a phase interpolation structure, and a delta-sigma structure in order to remove the spur.
The delta-sigma structure disperses the energy of spur generated in a pulse swallowing fraction ratio N frequency synthesizer and transforms the shape of the energy (noise shaping) to implement a high performance frequency synthesizer.
[Dual Modulus Fractional N]
FIG.
1
(
a
) is a block diagram for describing a basic factional type divider, and FIGS.
1
(
b
) and FIG.
1
(
c
) are waveforms for describing the operation and variations in the difference of the phases of the divider.
The structure of the basic fractional type divider in FIG.
1
(
a
) controls the dual modulus prescaler
1
to produce the division ratio such as below Equation 1 wherein the T
p+1
is a time section which has the 1/(P+1) division ratio and the T
P
is a time section which has the 1/P division ratio.
f
vco
=
[
N
+
T
P
+
1
T
P
+
T
P
+
1
]
·
f
ref
=
(
N
·
f
)
·
f
ref
[
Equation
1
]
In this process, however, variations in the phase generated in period of 1(.f)*f
ref
causes to modulate an oscillator through a charge pump and a loop filter, so that a high spur is generated at N*(.f)f
ref
(N is a positive integer) against the output center frequency of the oscillator. This spur is difficult to remove using the loop filter. Further, the sensitivity of a communication system is decreased by the spur near the output frequency of the oscillator.
The spur can be generated by a control voltage as follows. When the output of the oscillator is V
out
(t)=A(t)cos[w
0
t+&PHgr;(t)], the phase noise by the frequency modulation of a control signal Vc(t) can be expressed as follows:
V
out
(
t
)=
A·
cos[(&ohgr;
0
+K
VCO
·V
C
(
t
))·
t],
V
C
(
t
)=
A
m
·sin(&ohgr;
mt)
&ohgr;=&ohgr;
0
+K
VCO
·V
C
(
t
),
φ
0
=
∫
(
ω
0
+
K
VCO
·
V
C
(
t
)
)
ⅆ
t
=
ω
0
t
+
K
VCO
∫
-
∞
t
V
C
(
t
)
ⅆ
t
Therefore, V
out
(t) can be approximated as
V
out
(
t
)
≈
A
cos
w
0
t
-
A
m
·
A
·
K
VCO
ω
m
·
sin
ω
0
t
·
sin
ω
m
t
=
A
cos
ω
0
t
-
A
m
AK
VCO
2
ω
m
{
cos
(
ω
0
-
ω
m
)
t
+
cos
(
ω
0
+
ω
m
)
t
}
Therefore, spur is generated at to &ohgr;
0
±&ohgr;
m
.
[Multi-Modulus Fractional N]
The dual modulus fractional ratio N can be implemented into a first order delta-sigma. As the dual modulus fractional ratio N has the quantization level of /P and /(P+1) by one bit control, at this time, the energy of spur can be effectively dispersed and reduced. In general, the dual modulus fractional ratio N is implemented into a delta sigma of over third order. In case of designing the dual modulus fractional ratio N having a delta sigma of over third order, a delta-sigma modulator of a mash type that can obtain an effect of transformation of energy shape and can obtain high stability is usually applied to a frequency synthesizer. As an output of the modulator of a mash type is multi-bit, a multi-modulus prescaler is required in order for the dividing circuit to accept it. As a result, the dividing circuit requires complicated dividing unit and control unit.
A process of inducing the mash type structure is first described, and problems in the conventional multi-modulus dividing circuit is then described.
At first, over-sampling (quantization) is described. If quantization errors are white noise, the mean square value is:
e
r
m
s
2
=
1
Δ
∫
-
Δ
/
2
+
Δ
/
2
e
2
ⅆ
e
=
Δ
2
12
And if the quantized signal is sampled to f
S
=1/&igr;, the spectral density of a band is:
E
(
f
)
=
e
r
m
s
(
2
f
s
)
1
/
2
=
e
r
m
s
2
τ
Noise power of a signal band 0≦f≦f
0
is
n
0
2
=
∫
0
f
0
e
2
(
f
)
ⅆ
f
=
e
r
m
s
2
(
2
f
0
τ
)
=
e
r
m
s
2
OSR
, where
OSR=f
s
/2
f
0
=1/2
f
0
&igr;.
From the above results, it could be seen that over-sampling reduces the in-bands rms quantization noise(n
0
) to a square root of OSR. Further, it could be seen that the in-band noise is reduced by about 3 dB (corresponding to ½ bit resolution) when the sampling frequency is doubled.
Referring now to
FIGS. 2
a
~
FIG. 2
c,
first order delta-sigma modulation will be described. It was found that quantization using a simple over-sampling and filtering could improve SNR of 3 dB when the sampling frequency is made twice, while the in-band noise of a signal could be more reduced if feedback is introduced to the process.
FIGS. 2
a
~
FIG. 2
c
are block diagrams of the first order delta-sigma modulator.
FIG. 1
a
illustrates a first order delta-sigma modulator,
FIG. 2
b
illustrates an equivalent model of sampled data and
FIG. 2
c
illustrates a Z-domain model. Analysis for the first order delta-sigma can be expressed as follows:
S
(
I
)=
x
(
I
)−
y
(
I
),
w
(
I+
1)=
s
(
I
)+
w
(
I
),
y
(
I
)=
w
(
I
)
30
c
(
I
)
y
(
I
)=
x
(
I
)−
s
(
I
)=
x
(
I
)−[
w
(
I+
1)−
w
(
I
)]
w
(
I
)+
e
(
I
)=
x
(
I
)−
w
(
I+
1)+
w
(
I
)
w
(
I+
1)=
x
(
I
)−
e
(
I
)=
y
(
I+
1)−
e
(
I+
1)
y
(
I
)=
x
(
I−
1)+
e
(
I
)−
e
(
I−
1)
Therefore,
y
(
i
)=
x
i−1
+(
e
i
−e
i−1
).
In other words, the delta-sigma shown in
FIG. 2
causes to time-delay an original signal so that the original signal can be maintained intact, and reduce quantization errors by differentiation.
In order to obtain the spectral density of n
i
=(e
i
−e
i−1
), i.e., a noise due to modulation, Z-transform is performed. Thus, as N(z)=(1−z
−1
)E(z) and z=e
j&ohgr;&igr;
(&igr; is sampling frequency),
N
(
f
)
=
E
(
f
)
|
1
-
ⅇ
-
jωτ
|
=
2
e
r
m
s
2
τ
sin
(
ωτ
2
)
Therefore, it could be seen that the noise component of a low frequency can be reduced.
The noise power at the signal band is:
n
0
2
=
∫
0
f
0
&LeftBracketingBar;
N
(
f
)
&RightBracketingBar;
2
ⅆ
f
≈
e
r
m
s
2
π
2
3
(
2
f
0
τ
)
3
,
f
s
2
⪢
f
0
2
Also, the rms value is:
n
0
=
e
r
m
s
π
3
(
2
f
0
τ
)
3
/
2
=
Choi Jang Hong
Han Seon Ho
Jang Jae Hong
Yu Hyun Kyu
Blakely & Sokoloff, Taylor & Zafman
Electronics and Telecommunications Research Institute
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