Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-02-25
2001-09-25
Smith, Matthew (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S347000, C257S536000, C257S537000, C257S538000, C257S350000, C257S533000, C257S532000, C257S748000
Reexamination Certificate
active
06294834
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89100969, filed Jan. 21, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a structure of combined passive elements and logic circuits, and more particularly to a structure of combined passive elements and logic circuits on a SOI (Silicon On Insulator) wafer, which combined passive elements include resistors, inductors, capacitors and logic devices formed on a SOI wafer by using dual damascene technology, so that the layout area can be significantly decreased.
2. Description of the Related Art
In the semiconductor manufacture process, the damascene technology is an interconnects process, in which a groove is formed in an insulating layer and the groove is filled with metal to form a pin. Dual damascene is a multilevel interconnects process, in which not only a single groove, but also a via opening is formed.
For example, in the standard dual damascene process, an insulating layer is coated with a photoresist material. In this process, the photoresist layer is exposed to form a first mask with a via opening pattern, and the top of insulating layer is anisotropically etched to form the pattern. After removing the photoresist layer that has been transferred, the insulating layer is then coated with a photoresist material. In this process, the photoresist layer is exposed to form a second mask with the via opening alignment pattern. While etching the pin layer opening in the top of insulating layer, the via opening in the top of insulating layer is etched to the bottom of the insulating layer. When the etching process is finished, the via opening and the groove are then filled with metal. Dual damascene can be improved in a single metal damascene, because the dual damascene process allows the via opening and the groove to be filled with metal, simultaneously, so that many process steps can be eliminated. Therefore, the dual damascene process is a key technology to push the design rule for sub-0.18 um or lower technology.
The SOI technology is a new technology that has been employed throughout the wafer manufacturing industry. Compared to the device formed on a bulk wafer, the device formed on a SOI wafer has more advantages. For example, the SOI device has a lower power consumption, a low threshold operation and high performance advantages. These qualities are the result of manufacturing the silicon device in an isolated substrate so as to avoid the conventionally problematic inherent parasitic capacitance in the junction capacitor. Therefore, the reason for improving the SOI technology is to reduce parasitic capacitance so that the power consumption is minimized and operation speed in a specific dimension device is maximized. The use of a SOI wafer can disable the latch up effect in CMOS, and can decrease the soft error effect in MOS as well as increase the circuit operation speed.
In the conventional passive element fabrication process, which requires many complex steps, especially in the process in logic circuit of passive element, multilevel metal interconnects are a major key technology. As the process technology progresses to a level such as 0.18 um or less, device dimension is tends to be fabricated with the minimum size.
For a mixed mode circuit, many passive elements such as inductors, capacitors and resistors are required. Furthermore, due to products with increasingly smaller size, such as the notebook computer, fabrication of many devices with smaller dimensions is required. Hence, how to combine many different devices on a chip in order to reduce layout area is a present aspect of development.
SUMMARY OF THE INVENTION
The invention provides an improved structure of combined passive elements and logic circuits on a SOI wafer. The structure comprises a first oxide layer formed on a silicon substrate, a SOI substrate formed on the first oxide layer, a first shallow trench isolation layer formed on the first oxide layer and adjacent to the SOI substrate, a first single crystal Si resistor layer formed on the first oxide layer and adjacent to the first shallow trench isolation layer, a second shallow trench isolation layer formed on the first oxide layer and adjacent to the first single crystal Si resistor layer, a second single crystal Si resistor layer formed on the first oxide layer and adjacent to the second shallow trench isolation layer, a transistor formed on the SOI substrate, and a capacitor formed on the first single crystal Si resistor layer. The capacitor is composed of a lower electrode, a second oxide layer and a upper electrode, which are stacked sequentially, wherein the lower electrode is electrically connected to the first single crystal Si resistor layer. A dielectric layer over the silicon substrate, and a first via opening, a second via opening, a third via opening and a fourth via opening are formed in the dielectric layer. The first via opening is filled with a first multilevel interconnects layer, which is electrically connected to the second single crystal Si resistor layer electrically. The second via opening is filled with a second multilevel interconnects layer, which is electrically connected to the upper electrode of the capacitor. The third via opening is filled with a third multilevel interconnects layer and is electrically connected to the lower electrode of the capacitor. The fourth via opening is filled with a fourth multilevel interconnects layer, which is electrically connected to the third multilevel interconnects layer and the gate of the transistor.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a new structure of combined passive elements and logic circuits on a SOI wafer, in which, by combining passive elements (including a resistor, an inductor and a capacitor) with a logic device on a SOI wafer with copper or aluminum dual damascene technology, an extremely thick inductor can be formed vto reduce the resistance of the inductor effectively, while simultaneously reducing the layout area. The invention is compatible with conventional VLSI technology without increasing number of masks or process steps. Furthermore, because the resistor of the invention is composed of single crystal Si, the resistor has high stability and low noise. Therefore, the structure according to the invention is suitable for RF device design and also is suitable for System On Chip design.
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Lin Chih-Yung
Yeh Wen-Kuan
Luu Chuong A
Smith Matthew
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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