Structure of chip on chip mounting preventing from crosstalk noi

Details Structure of chip on chip mounting preventing from crosstalk noi Structure of chip on chip mounting preventing from crosstalk noi

1996-04-23

1998-10-13

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

257686, 257659, 257660, H01L 23552, H01L 2348, H01L 2302

Patent

active

058216251

ABSTRACT:
The present invention reduces crosstalk, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip 1 having a first electrode pad 2 and a first wiring layer 9 in the main surface, and a second semiconductor chip 5 having a second electrode pad 6 and a second wiring layer 10 in the main surface confronting the first semiconductor chip. A bump 4 is provided for electrically coupling the first electrode pad 2 and the second electrode pad 6 together. An insulation layer 8 is disposed between the main surfaces of first semiconductor chip 1 and second semiconductor chip 5. An electro-conductive layer 7 is disposed between the main confronting surfaces of the first semiconductor chip and the second semiconductor chip.

REFERENCES:
patent: 4763188 (1988-08-01), Johnson
patent: 4811082 (1989-03-01), Jacobs et al.
patent: 5508565 (1996-04-01), Hatakeyama et al.
patent: 5596225 (1997-01-01), Mathew et al.
patent: 5656856 (1997-08-01), Kweon

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