Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Patent
1991-12-26
1994-02-22
Picard, Leo P.
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
257775, H05K 100
Patent
active
052889483
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a structure of a semiconductor chip.
BACKGROUND OF THE INVENTION
Recently, it has become popular to package semiconductor devices such as, for example, IC or LSI devices using a resin instead of a ceramic material.
Conventionally, encapsulating a semiconductor chip by use of resin is performed by fixing, in a mold, a lead frame having the semiconductor chip mounted thereon and by flowing a sealing resin thereinto having a high temperature of approximately 170.degree. C. When the resulting mold has been cooled down to a room temperature, since the silicon, which is a material constituting the chip, has a small thermal expansion coefficient and the sealing resin has a thermal expansion coefficient greater than that of silicon, the surface of the chip comes to receive a stress acting toward a center thereof due to shrinkage of the resin. As a result, a sliding phenomenon takes place in which an aluminum conductive layer having a large width, such as a high voltage power source conductive layer or a ground conductive layer, is forcibly biased toward the center of the chip. Such a phenomenon occurs also when cyclic temperature tests are performed.
To prevent the occurrence of the sliding phenomenon of the aluminum conductive layer, some countermeasures have been proposed in Japanese Laid Open Patent Nos. 62-111451, 62-174948 or 63-211648 which disclose that the aluminum conductive layer width is made narrow to constitute the conductive layers by a plurality of the narrower layer, or that the substantial width of the conductive layer is made small by providing a slit or slits in the layer, etc.
However, if the conductive layer or the ground conductive layer is made excessively small in width, electromigration will inconveniently occur. In addition, even if the aluminum conductive layer is divided into several parts, the effect of preventing the occurrence of the aluminum conductive layer sliding phenomenon will vanish if the divided conductive layer portion is made relatively large in width.
SUMMARY OF THE INVENTION
The present invention relates to a conductive layer structure of a semiconductor chip molded with an encapsulating resin, which has a relatively wide aluminum conductive layer divided into a plurality of narrower layer portions, and at least a part of which has a width of greater than 10 .mu.m but smaller than 40 .mu.m.
The present invention is directed to providing a multilayer conductive layer structure of a semiconductor chip having a portion of intersection between a lower conductive layer relatively small in width and an upper aluminum conductive layer relatively large in width, wherein the chip is molded with a sealing resin, the upper aluminum conductive layer is formed with a slit at a position spaced 10 .mu.m to 50 .mu.m from that side of the intersection portion between the lower conductive layer and the upper conductive layer which is located nearer to a center of the chip, and the position is in an extended region of a region formed through connection between the center of the chip and the side of the intersection portion.
Also, the present invention is directed to providing a conductive layer structure of a semiconductor chip having an intermediate insulating layer, capable of absorbing moisture, between the lower metal conductive layer and the upper metal conductive layer, the upper metal conductive layer being provided so that the width may be in a range of 10 .mu.m to 40 .mu.m at a position on the lower conductive layer.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a partial plan view of a semiconductor chip illustrating a first embodiment in accordance with the present invention.
FIG. 2 is a partial plan view of a semiconductor chip illustrating another example of the first embodiment in accordance with the present invention.
FIG. 3(a) is a partial plan view of a conductor layer having a slit.
FIG. 3(b) is a graph showing the relationship between the proportion of area occupied in the conductive layer of FIG. 3(a) by a slit an
Fukuda Yasuhiro
Hirashita Norio
Kobayakawa Masayuki
Matsuo Mitsuhiro
Saito Minoru
Figlin Cheryl R.
OKI Electric Industry Co., Ltd.
Picard Leo P.
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