Structure of a dual damascene

Details Structure of a dual damascene Structure of a dual damascene

1998-10-02

2000-08-01

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257643, H01L 23535

Patent

active

060970936

ABSTRACT:
A dual damascene structure includes a semiconductor substrate, a metal-oxide-semiconductor (MOS) transistor formed on the substrate and a metal layer. The metal layer is electrically connected to the conducting regions of the MOS transistor through interconnect. The metal layer further includes first metal spacing regions and second metal spacing regions, wherein the width of a first metal spacing region is about 1 to 10 times of the linewidth of the device, and the width of a second spacing region is about 0.8 to 1.2 times of the linewidth of the device. The first metal spacing regions includes a high-permittivity dielectric for a better thermal transferring rate, and the second spacing regions includes a low-permittivity dielectric for a shorter resistance-capacitance delay.

REFERENCES:
patent: 5442237 (1995-08-01), Hughes et al.
patent: 5565707 (1996-10-01), Colgan et al.
patent: 5659201 (1997-08-01), Wollesen

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