Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-03-13
2004-05-04
Cuneo, Kamand (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000, C174S258000
Reexamination Certificate
active
06730857
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to providing a structure having circuitry features and in particular to embedded flush circuitry features. The present invention is especially advantageous for fabricating buried interconnection levels that are in close proximity to one another in a printed circuit board structure.
BACKGROUND OF THE INVENTION
Printed circuit boards find a wide variety of uses in the electronics industry with the demand for high performance, printed wiring, or circuit boards for various applications steadily increasing. For instance, the complexity, compactness and electrical performance requirements of printed boards have significantly increased over the last several years. The demands on printed circuit boards require high density packaging, fine interconnection, multilayer formation and the need to form a plurality of interconnections in a small space.
Currently, printed circuit board interconnection levels are built on top of a dielectric thin film layer. Circuitry features are formed using photolithographic and subtractive etch techniques. In a typical method, a metallic foil and especially copper foil is laminated to the substrate followed by using photolithographic and subtractive etching to create the circuitry. The copper foil includes a roughened or dendritic backside surface for inducing mechanical adhesion to the substrate. Smooth copper layers do not adequately bond without an auxiliary bonding agent.
Great difficulties exist in adequately etching dendrites especially when dealing with small spaces. Moreover, along with the concern areated by dendrites, the width of the lines (e.g. about 0.5 mils wide), and photolithographic issues (e.g. resolution of fine features, 0.7 mil wire with 1.1 mil space, in a thin photo resist film), and subtractive etch undercut and pad rounding, render clearly and fully resolving small line spaces such as the 1.8 mil pitch features presently desired very difficult. Additionally, this subtractive etch approach results in unprotected circuitry features referred to as “skyscrapers” that extend above an underlying plane of dielectric barrier material.
In many structures, it is important to plate another metal such as gold or nickel-gold onto the copper circuitry. The “skyscraper” structure causes a problem of bridging or shorting between lines especially where there exist closely spaced fingers.
SUMMARY OF THE INVENTION
The present invention provides for obtaining a structure having dense embedded flush circuitry features. The present invention makes it possible to create circuitry features that are much more densely configured than those fabricated using current methods. This is made possible since the final structure is a circuitry feature having dielectric regions and conductive features that are coplanar.
In particular, the present invention relates to a structure comprising a first dielectric layer of a polymeric material having a first top surface; a second dielectric layer of polymeric material on said first top surface of said first dielectric layer of a polymeric material, having a second top surface, said second layer of polymeric material also having trench features therein; electrically conductive material deposited in said trench features forming electrically conductive circuit lines and being substantially flush with said second top surface of said second dielectric layer of polymeric material.
Another aspect of the present invention relates to a method for fabricating a structure having embedded substantially flush circuit features. The method comprises providing a first dielectric layer of a polymeric material with a top surface; depositing a second dielectric layer of polymeric material on said top surface of first dielectric layer of a polymeric material, said second dielectric layer of polymeric material also having a second top surface; defining trench features with sidewalls and bottoms, substantially in said second dielectric layer of polymeric material; providing a seed layer only on said sidewalls bottoms of said trench features; depositing electrically conductive material in said trench features such that said electrically conductive material is substantially coplanar with said top surface of said second dielectric layer of polymeric material.
A still further aspect of the present invention related to another method for fabricating a structure having embedded substantially flush circuitry features which method comprises:
providing a first layer of polymer resin having a metal dispersed therein and having a top surface;
depositing a second dielectric layer of a dielectric polymeric material on said top surface of said first layer of polymer resin, said second dielectric layer of a dielectric polymeric material also having a second top surface;
defining trench features with sidewalls and bottoms, substantially in said second dielectric layer of a dielectric polymeric material and into said first layer of dielectric polymer resin and thereby exposing metal in sidewalls and bottoms of said trench features to provide a seed layer;
depositing electrically conductive material in said trench features such that the electrically conductive material is substantially coplanar with said second top surface of said second dielectric layer of dielectric polymeric material.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
The present invention also relates to structures obtained by the above-disclosed processes.
REFERENCES:
patent: 3149265 (1964-09-01), Thorn
patent: 3324014 (1967-06-01), Modjeska
patent: 4306925 (1981-12-01), Lebow et al.
patent: 4875282 (1989-10-01), Leibowitz
patent: 4915983 (1990-04-01), Lake et al.
patent: 5004640 (1991-04-01), Nakatani et al.
patent: 5456817 (1995-10-01), Hino et al.
patent: 5620800 (1997-04-01), De Leeuw et al.
patent: 5647966 (1997-07-01), Uriu et al.
patent: 5714050 (1998-02-01), Akiba et al.
patent: 5821168 (1998-10-01), Jain
patent: 5822850 (1998-10-01), Odaira et al.
patent: 5830533 (1998-11-01), Lin et al.
patent: 5863405 (1999-01-01), Miyashita
patent: 5891513 (1999-04-01), Dubin et al.
patent: 5976393 (1999-11-01), Abe
patent: 6183669 (2001-02-01), Kunota et al.
patent: 6335077 (2002-01-01), Tani et al.
patent: 0935407 (1999-08-01), None
patent: WO99/47731 (1999-09-01), None
Patent Abstracts of Japan, Application No. 09068383, 10/98, Sony Corp., Manufacture of Printed Wiring Board.
Konrad John Joseph
McKeveny Jeffrey
Wilson James Warren
Connolly Bove & Lodge & Hutz LLP
Cuneo Kamand
International Business Machines - Corporation
Patel I B
Samodovitz Arthur J.
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