Structure for updating a block of memory cells in a flash...

Details Structure for updating a block of memory cells in a flash... Structure for updating a block of memory cells in a flash...

2005-07-26

2005-07-26

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290, C365S189070

Reexamination Certificate

active

06922362

ABSTRACT:
An electronic circuit structure for updating a block of memory cells in a flash memory device, the memory cells storing a current value, wherein the structure includes a data latch for receiving a new value to be written on the memory cells, a controller for erasing the block of memory cells simultaneously, and programming load bank coupled to the controller and the data latch for programming the memory cells individually; the structure further includes control logic coupled to the controller for enabling the controller and for enabling the programming load bank according to a comparison between the new value and the current value.

REFERENCES:
patent: 4763305 (1988-08-01), Kuo
patent: 5754567 (1998-05-01), Norman
patent: 6157570 (2000-12-01), Nachumovsky

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