Structure for testing NAND flash memory and method of...

Details Structure for testing NAND flash memory and method of... Structure for testing NAND flash memory and method of...

2006-04-18

2006-04-18

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185050, C365S201000

Reexamination Certificate

active

07031190

ABSTRACT:
Provided is a structure for testing a NAND flash memory including a first string select transistor for controlling transfer of a voltage inputted via a first bit line; a first string having a plurality of flash memory cells, connected between the first string select transistor and a first source select transistor, and maintaining a program or erase state depending on a voltage inputted thereto; a second string select transistor for controlling transfer of a voltage inputted via a second bit line; a second string having a plurality of flash memory cells, connected between the second string select transistor and a second source select transistor, and maintaining the program or erase state depending on a voltage inputted thereto; and a measurement pad connected to a point where the first or second string select transistor and the flash memory cell are connected.

REFERENCES:
patent: 6175523 (2001-01-01), Yang et al.
patent: 6240020 (2001-05-01), Yang et al.
patent: 6252800 (2001-06-01), Chida

Affiliated with

Also associated with

Rating

Structure for testing NAND flash memory and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Structure for testing NAND flash memory and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Structure for testing NAND flash memory and method of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3596646