Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-02-16
2001-04-10
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C327S525000, C327S564000
Reexamination Certificate
active
06215170
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the design of integrated semiconductor circuits and, more particularly, to a parallel capacitor and diode structure used in a device for selecting design options in an integrated circuit.
BACKGROUND OF THE INVENTION
It is known that, during the design of a complex integrated circuit, it is often difficult to establish with certainty beforehand the most advantageous circuit configuration or the most suitable component to achieve a predetermined functional effect. For example, it may be difficult, if not impossible, to evaluate the best time constant for a certain function, or the most appropriate intervention threshold for a given circuit, or the ideal current which a current-generator should supply. Moreover, it may also be useful to test a section of the integrated circuit in several different operative conditions, for example, with and without a network for correcting a parameter, in order to evaluate the effect of the correction, as in the case of an “offset”-canceling circuit, the exclusion of which would allow the magnitude of the “offset” to be evaluated.
It is also known that, during the design of an integrated circuit, it may be convenient to leave the selection between several variants of the circuit configurations and/or parameters open, to permit the production of integrated circuits the general functional characteristics of which are substantially identical, but which satisfy slightly different applicational requirements.
Thus, to allow for the “design options” described above, it is often necessary, at the design stage, to provide for modifiable connections or for selectively addressable memory cells or registers which enable the inputs of associated circuit units to be modified so as to adopt different operative states in dependence on the states of the aforesaid modifiable connections or of the memory cells or registers.
The various options are then tested and, of these, the one which offers the functional characteristics closest to those desired is selected and the final topography of the integrated circuit to be put into production is consequently defined.
The known techniques for satisfying the design requirements described above provide for the use of terminals of the device by means of which connection may or may not be established, of fuses within the integrated circuit which can be broken by means of high currents applied between suitable terminals of the integrated circuit, of EPROM cells, of programmable register cells, or of different metallization masks for the various design options. All of these techniques, except for the last mentioned, take up quite large areas of the integrated circuit; in particular, the use of terminals of the device requires the formation of contact pads which, as is known, necessarily have large dimensions; fuses require wide metal connecting strips because of the high currents necessary to break them and are also unreliable; in addition to the space which they take up, EPROM cells also require a special manufacturing process. In any case, for all these techniques, it is necessary to provide piloting signals which, in order to control the integrated circuit, naturally have to be conducted to the corresponding points by means of suitable metal tracks which are also very bulky.
As is known to a designer of integrated circuits, after the most favorable design options have been defined, modification of the topography of the integrated circuit in order to recover the areas intended for the test components and/or connections often cannot be accomplished, and these areas are therefore inevitably lost, detracting from the compactness of the final integrated structure.
As regards the technique which provides for different metallization masks for the various options, that is, variations in the mask for the formation of the last layer of connections in the sequence of steps of the manufacturing process, the problem is not the area taken up since, in this case, additional components or connections are not necessary, but, rather, the cost and the time necessary to put it into practice. In fact, each variant to be tested corresponds to a different mask, which itself is quite expensive, and to the manufacture of a batch of test chips, which requires a very long waiting time to evaluate the test. This technique is therefore suitable only when the number of variants to be tested is very low.
SUMMARY OF THE INVENTION
An object of the present invention is to propose a device for selecting between design options in an integrated circuit which is reliable, which has practically zero power consumption, which takes up a very small area, which does not require additional masks or process steps, and which is usable without limitations on the number of variants to be tested.
Another object of the invention is to provide a structure having a diode and capacitor coupled in parallel that can be implemented in standard bipolar technology as well as in CMOS technology containing an N or P well.
According to one aspect of the present invention, an integrated circuit is provided for selecting one of a number of design configurations for an integrated device. The circuit includes first and second supply terminals and a substrate having a first conductivity. A plurality of semiconductor layers are formed on said substrate and have a set of integrated circuit components formed therein. A circuit unit of the set of components is operable to be configured in one of a number of configurations in response to a signal. A removable link of the set of components has a first link terminal coupled to the first supply terminal. A buffer of the set of components has a buffer input terminal coupled to a second link terminal and a buffer output terminal coupled to the circuit unit. The buffer is operable to generate said signal at said buffer output terminal. An insulator is provided over a portion of said substrate being patterned to expose first and second direct substrate contacts. The first contact is coupled to the second link terminal and the second contact is coupled to the second supply terminal formed on the insulator between the first and second contacts. A first region of the first conductivity type in a surface area of the substrate is formed under the first contact. A second region of a second conductivity type is formed under the insulator and extends past the second contact. The second region is laterally spaced from the first region, and the first and second regions and insulator form a capacitive element in parallel with a diode within the integrated circuit.
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“Precision” “Power-on-Reset′ Control Circuit,”IBM Technical Disclosure Bulletin,vol. 32, No. 7, Dec. 1989, pp. 159-60.
Blanchard Richard A.
Confalonieri Pierangelo
Carlson David V.
Galanthay Theodore E.
Jorgenson Lisa K.
STMicroelectronics Inc.
Tran Minh Loan
LandOfFree
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