Structure for scheduler pipeline design for hierarchical...

Details Structure for scheduler pipeline design for hierarchical... Structure for scheduler pipeline design for hierarchical...

2004-02-05

2008-11-25

Vu, Huy D. (Department: 2616)

Multiplex communications

Data flow congestion prevention or control

Control of data admission to the network

C370S229000, C370S231000, C370S235000, C370S412000

Reexamination Certificate

active

07457241

ABSTRACT:
A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.

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