Structure for reducing stress for vias and fabricating...

Details Structure for reducing stress for vias and fabricating... Structure for reducing stress for vias and fabricating...

2006-04-26

2009-06-09

Nguyen, Cuong Q (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S774000

Reexamination Certificate

active

07545039

ABSTRACT:
A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.

REFERENCES:
patent: 6586822 (2003-07-01), Vu
patent: 6586836 (2003-07-01), Ma et al.
patent: 6759750 (2004-07-01), Shue et al.

Affiliated with

Also associated with

Rating

Structure for reducing stress for vias and fabricating... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Structure for reducing stress for vias and fabricating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Structure for reducing stress for vias and fabricating... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4101417