Structure for reduced gate capacitance in a JFET

Details Structure for reduced gate capacitance in a JFET Structure for reduced gate capacitance in a JFET

2007-09-11

2007-09-11

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S264000, C257S268000, C257S266000, C257S134000

Reexamination Certificate

active

10158326

ABSTRACT:
A junction field effect transistor (JFET) with a reduced gate capacitance. A gate definition spacer is formed on the wall of an etched trench to establish the lateral extent of an implanted gate region for a JFET. After implant, the gate is annealed. In addition to controlling the final junction geometry and thereby reducing the junction capacitance by establishing the lateral extent of the implanted gate region, the gate definition spacer also limits the available diffusion paths for the implanted dopant species during anneal. Also, the gate definition spacer defines the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.

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