Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing
Reexamination Certificate
2011-07-26
2011-07-26
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
C710S034000, C710S113000, C370S232000, C370S393000
Reexamination Certificate
active
07987437
ABSTRACT:
A design structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization is disclosed. In one embodiment of the design structure, a method in a computer-aided design system includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant.
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IBM—64-Bit Processor Local Bus, Architecture Specifications Version 3.5; May 2001, 122 pgs.
Drerup Bernard C.
Nicholas Richard
Chiang Jack
Dillon & Yudell LLP
Dimyan Magid Y
International Business Machines - Corporation
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