Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1997-11-10
2002-08-06
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S775000, C257S780000, C257S783000, C228S180220, C361S773000, C361S774000
Reexamination Certificate
active
06429516
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a structure for mounting a bare chip and, more particularly, to bare chip mounting method and structure in which a bare chip can easily be removed from a circuit board, if such a bare chip is an unacceptable one, by disposing an interposer between the bare chip and the circuit board when the bare chip is to be mounted on the circuit board. The present invention also relates to bare chip mounting method and structure in which electrical characteristics of the bare chip can easily be examined before such a bare chip is mounted on the circuit board.
2. Description of the Related Art
In a conventional method or structure for mounting a bare chip on a circuit board, if it is found that the bare chip is unacceptable after it is mounted, it is necessary to remove the bare chip from the circuit board and to change it for a new one. However, when the bare chip is changed, the circuit board is sometimes damaged by the changing operation and sometimes the circuit board can no longer be used.
For example, as shown in FIG.
4
(
a
), Japanese Unexamined Patent Publication No. 3-19251 discloses a bare chip mounting structure in which a bare chip
3
is first mounted on predetermined conductive electrodes
2
of a circuit board
1
by a face-down bonding using a solution conductive adhesive containing two solutions having different glass transition points and then one of the solutions in the solution conductive adhesive having a lower glass transition point is evaporated by any method, such as heating or the like.
As shown in FIG.
4
(
b
), as time passes, the contact resistance of the bare chip
3
is reduced as the solution in the solution conductive adhesive is evaporated and, when the time has expired at T, the electrical resistance becomes constant. After that, the bare chip
3
is subjected to an electrical examination and, if any unaccepted bare chip is found, such a bare chip is removed from the circuit board
1
, so that only an acceptable bare chip is finally mounted and secured on the circuit board by finally curing the solution conductive adhesive.
In this bare chip mounting method, however, since the bare chip
3
is adhered only to the electrodes
2
by means of the conductive adhesive
4
, the strength of mounting is not at a reliable level, although the bare chip
3
can easily be removed if it is found to be an unacceptable one.
Another bare chip mounting structure is disclosed in Japanese Unexamined Patent Publication No. 6-69280 in which, as shown in FIG.
5
(
a
), a thermosetting palladium conductive resin material is coated on pads
5
arranged on a circuit board
1
using a mask and the thermosetting palladium conductive resin material is then cured by heating to form bumps
6
.
Then, as shown in FIG.
5
(
b
), a thermosetting synthetic resin
7
a
which is in state of gel at room temperature is attached to the surfaces where the pads
5
are arranged and the electrodes
3
a
of the bare chip
3
are positioned with respect to the bumps
6
. Then, the bare chip
3
is pushed in the direction indicated by an arrow B and heated, for example, to a temperature of 110 to 150° C. in such a manner that, as shown in FIG.
5
(
c
), the gel-like synthetic resin
7
a
is cured to form an insulating layer
7
and thus the bare chip
3
is rigidly secured to the circuit board
1
and the bumps
6
are simultaneously attached to the pads, so that the bare chip
3
is finally mounted on the circuit board
1
.
The bare chip
3
is subjected to an examination for electrical characteristics. If the bare chip
3
is unacceptable, it can easily be removed from the circuit board, for example, by heating the circuit board to a temperature of 150 to 200° C. which is higher than the above-mentioned heating temperature to soften the insulating layer
7
.
In this bare chip mounting method, the examination for electrical characteristics is usually performed after the bare chip is mounted on the circuit board. However, such an examination can also be performed, for a bare chip itself, before the bare chip is mounted on the circuit board. In this case, in the conventional testing device for electrical properties of the bare chip, as shown in
FIG. 6
, a plurality of probe pins
8
must be guided so as to be in conformity with the pitch of the electrodes of the bare chip. In still another prior art, a socket having contact pins which are arranged at the same pitch as that of the electrodes of the bare chip, is used.
In the above-mentioned bare chip mounting method described with reference to
FIG. 6
, since the probe pins are arranged so as to be in conformity with the pitch of the electrodes of the bare chip, the probe pins must be long and therefore a test for high frequency characteristics cannot be fully realized. In addition, a socket having contact pins which are arranged at the same pitch as that of the electrodes of the bare chip is expensive and a durability cannot be expected since the contact pins must be fine.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method and a structure, for mounting a bare chip on a circuit board, in which reliability is maintained and, on the other hand, changing of a bare chip can easily be carried out.
Another object of the present invention is to provide a method and a structure, for mounting a bare chip on a circuit board, in which an examination of the bare chip can easily be carried out before the bare chip is fixedly mounted on the circuit board.
According to the present invention, there is provided a bare chip mounting structure comprising: a bare chip having inlet or outlet terminals; an interposer having openings at positions corresponding to the inlet or outlet terminals of the bare chip; and a circuit board having conductive pads wherein the bare chip is mounted on the circuit board by means of the interposer in such a manner that the inlet or outlet terminals are electrically connected to the conductive pads of the circuit board through the openings in the interposer.
In one embodiment, each of the openings of the interposer has an inner wall thereof which is plated with an electrically conductive metal.
In another embodiment, each of the inlet or outlet terminals is a metal bump having at least two steps comprising a base portion having a larger diameter and a tip end portion having a smaller diameter.
In still another embodiment, the interposer has at least one pad for the purpose of testing and a lead line connecting the pad to the inlet or outlet terminal of the bare chip when the bare chip is mounted on the circuit board.
In further embodiment, a thermosetting resin adhesive is filled between the bare chip and the interposer and between the interposer and the circuit board.
According to another aspect of the present invention, there is provided with a method of mounting a bare chip on a circuit board, the method comprising the following steps of: adhering an interposer, having openings at positions corresponding to inlet or outlet terminals of the bare chip, to a circuit board having conductive pads in such a manner that the openings of the interposer are aligned with the conductive pads of the circuit board; and mounting the bare chip on the circuit board in such a manner that the inlet or outlet terminals of the bare chip electrically contact the conductive pads of the circuit board through the openings of the interposer.
In still another aspect of the present invention, there is provided a method for mounting a bare chip on a circuit board, the method comprising the following steps of: adhering an interposer, having openings at positions corresponding to inlet or outlet terminals of the bare chip and each of the openings having inner wall plated with electrically conductive metal, to a circuit board having conductive pads in such a manner that the openings of the interposer are aligned with the conductive pads of the circuit board;
mounting the bare chip on the circuit board in such a manner that the inlet or out
Armstrong Westerman & Hattori, LLP
Chambliss Alonzo
Fujitsu Limited
Talbott David L.
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