Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1999-03-26
2001-11-13
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S499000, C257S510000, C438S296000, C438S353000, C438S354000, C438S355000
Reexamination Certificate
active
06316815
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a trench isolation structure for isolating integrated circuits, and particularly to a method for forming a trench isolation structure with a dielectric stud filling and spanning a trench in a semiconductor substrate.
BACKGROUND OF THE INVENTION
To keep pace with the increasing density of active devices in ICs (integrated circuits), development of new isolation schems plays a critically important role in fabricating relatively modernized ICs. A promising alternative among the new isolation schemes is a trench isolation structure and the process for making it.
However, a conventional or prior-art trench isolation structure in ICs usually suffers problems such as current leakage at the corners of a trench, resulting in significant device current leakage in ICs, especially when there's any recess in the trench isolation structure. Consequently various raised trench isolation structures have been suggested as keys to the problem, among which one is the art disclosed in U.S. Pat. No. 5,733,383 and characterized by having a self-aligned cap or dome that is above the upper surface of the semiconductor substrate of an IC device and is formed through several processing steps to first construct a raised trench isolation structure
4
as shown in
FIG. 1
, and then to deposit insulating material
5
as shown in
FIG. 2
conforming to the profile of the raised trench isolation structure
4
shown in FIG.
2
. The insulating material
5
according to the prior art is thereafter processed by a step of dry etching to form spacers
6
as shown in
FIG. 3
, which are then preferably processed by a step of wet pad oxide etching to form a structure having a cap or dome as shown in FIG.
4
.
It can be seen that the art suggested by U.S. Pat. No. 5,733,383 requires insulating material
5
to be deposited conforming to the profile of the structure and then etched in a critically sophisticated way in order to form the trench isolation structure shown in FIG.
4
. The process for forming such a structure may rely too much on experience or even good luck, leaving a need of developing an alternative scheme for isolating ICs on the basis of trench structure, leading to the development of the present invention.
SUMMARY OF THE PRESENT INVENTION
Objects:
It is a primary object of the invention to provide a method for conveniently and systematically forming a trench isolation structure for isolating ICs fabricated in a semiconductor substrate. It is another object of the invention to provide ICs with a trench isolation structure formed on the basis of insulating dielectric filling and spanning a trench in the semiconductor substrate on which the ICs are fabricated.
It is a further object of the invention to provide a trench isolation structure and method for systematically forming the structure which can significantly reduce the leakage current at trench corners of the trench isolation structure in a semiconductor substrate.
Introduction to The Invention:
The present invention is featured by a dielectric stud filling and spanning a trench in a semiconductor substrate in order to provide requisite isolation for the ICs fabricated in the semiconductor substrate, and to significantly reduce current leakage at comers of the isolation trench. The dielectric stud is made of insulating material or any material capable of electrically isolating integrated circuits.
One aspect of the method provided by the invention for forming such a trench isolation structure in a semiconductor substrate is characterized by the steps of:
(a). forming a first layer overlying the semiconductor substrate, with the first layer functioning as a buffer layer (stress-release layer) which may be a pad oxide layer comprising silicon oxide typically formed by thermal oxidation;
(b).forming a second layer overlying the first layer (buffer layer), with the second layer functioning as an oxidation barrier layer which may be made of silicon nitride;
(c).patterning the second layer and the first layer to form an exposed portion of the semiconductor substrate, while retaining portions of the first and second layers over device areas, i.e., conventional techniques such as one using photolithogrephic skill, photoresist layering, and anisotropic plasma etching are used to etch at least an opening in the first layer and second layer over the areas on the semiconductor substrate where the trench is to be formed, and with used photoresist removed, for example, by plasma etching the patterned second layer (patterned silicon nitride layer) is used to partially etch into the semiconductor substrate from the exposed portion thereof to form a trench that is to surround and electrically isolate device areas of the ICs;
(d).thermally oxidizing the exposed surface of the trench to form a liner layer covering the exposed surface of the trench;
(e).coating a photoresist layer filling the trench and overlying the patterned second layer;
(f).removing a portion of the photoresist layer to expose an upper surface of a trench adjacent second layer portion, the trench adjacent second layer portion being the portion of the patterned second layer adjacent to the trench, the upper surface of the trench adjacent second layer portion being the surface opposite to the surface between the semiconductor substrate and the trench adjacent second layer portion, i.e., the upper surface of the portion of the patterned second layer which is beside the lengthwise edges of the trench is exposed, the edges of the trench being the intersections between the sidewalls (the portions of the trench's surface which are perpendicular to the upper surface of the semiconductor substrate) of the trench and the second layer;
(g).etching, by plasma for example, the trench adjacent second layer portion from its exposed upper surface to leave a remaining second layer portion;
(h).removing the photoresist layer remained;
(i).depositing a type of dielectric such as insulating material to fill the trench and to form a dielectric stud defined by the trench, the patterned first layer, and the remaining second layer portion, i.e., depositing the dielectric to fill the space surrounded by the trench, the patterned first layer, and the remaining second layer portion;
(j).removing the remaining second layer portion to leave an exposed portion of the patterned first layer;
(k).removing the exposed portion of the patterned first layer; a dielectric stud filling the trench and spanning the trench to extend laterally beyond the trench (i.e., to extend over the lengthwise edges of the trench) is thus formed, thereby a trench isolation structure in the shape of a stud is achieved for isolating ICs while significantly reducing current leakage at corners of the trench.
In step (i) of the method suggested by the invention and described above, the dielectric may be deposited so as to extend onto the upper surface of the remaining second layer portion, and then processed by CMP (chemical/mechanical polishing) to be aligned with the upper surface of the remaining second layer portion.
In step (k) of the method suggested by the invention and described above, the dielectric stud spanning the trench to extend laterally beyond the trench may be partially removed without affecting the formation of a usable trench isolation structure as long as it still spans the trench to extend over the lengthwise edges of the trench.
The structure provided by the invention for isolating integrated circuits fabricated in a semiconductor substrate is characterized by comprising:
a trench formed in the semiconductor substrate by, for example, patterning a dielectric layer which overlies a substrate upper surface of the semiconductor substrate to form an exposed portion of the substrate upper surface, and by etching the exposed portion of the substrate upper surface, the dielectric layer being preferably a layer composed of a buffer layer and an oxidation barrier layer, or the dielectric layer being preferably a layer capable of functioning as both the buffer layer and the oxida
Intellectual Property Solutions, P.L.L.C.
Lee G.
Smith Matthew
Vanguard International Semiconductor Corporation
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