Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1999-04-30
2000-11-07
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257513, 257514, 257515, 438221, 438224, H01L 2900
Patent
active
061440868
ABSTRACT:
A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at a second depth which is deeper than the first depth. The n- and p-wells are formed on either side of the trench. A highly doped region is formed in the substrate underneath the second substantially horizontal surface of the trench. The highly doped region abuts both the first and the second wells and extends the isolation of the trench.
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Brown Jeffrey Scott
Gauthier Jr. Robert J.
Mann Randy William
Voldman Steven Howard
International Business Machines - Corporation
Owens Douglas W.
Thomas Tom
LandOfFree
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