Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-04-05
2004-12-07
Chambliss, Alonzo (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S653000, C438S014000
Reexamination Certificate
active
06828647
ABSTRACT:
FIELD OF THE INVENTION
This invention is a technique useful in the manufacture of integrated circuits and, more particularly, relates to determining the edges of wells of one conductivity type formed in regions of opposite conductivity type in semiconductor wafers in which the integrated circuits are being formed.
BACKGROUND OF THE INVENTION
Many of todays integrated circuit devices have semiconductor bodies (substrates) of one conductivity type and regions (wells) formed therein of the opposite conductivity type. Generally these wells are formed by diffusion or implantation processes using, for control, masks that have been patterned by photolithography. Typically the wells are regions that extend horizontally between one and ten microns wide. It is generally important to determine the edges of such wells with an accuracy of about plus or minus ten nanometers. However, photolithographic processes are subject to process variations that make it difficult to establish with the desired high accuracy the precise edges of the wells formed, especially when such edges underlie an insulating layer. In particular, it is difficult to locate precisely the edge of the photoresist mask that is used to locate the edges of the wells being formed. These uncertainties in knowledge of where the well edges are can cause complications in the processing of large scale integrated circuits where some circuit elements are to be positioned near edges in the wells. The process of determining accurately the location of well edges is complicated when, at the stage at which the edges need to be located, the well edges may be only 100 nanometers wide and covered with an insulating layer that makes surface probing ineffective, and also the edge determination needs to be done in a manner that is non-destructive. Moreover, the fact that the well edges are buried below insulating surface layers also make optical probing techniques burdensome.
The present invention provides a new approach that should be less burdensome than prior techniques. In particular, the approach is one that should be more readily automated to provide edge information for all the chips of a wafer.
SUMMARY OF THE INVENTION
Broadly the invention provides a technique for locating electrically the edge of a vertical p-n junction that underlies an insulating layer in a semiconductor body.
Basically it involves initially providing at the surface of a region of the semiconductor body of one conducting type a plurality of conductive stripes that are of the opposite conductivity type and are designed to extend below the later-to-be-formed overlying insulating layer to varying extents and of which at least one extends across the later-to-be-formed junction edge that is to be located. Stripes that extend across the junction edge are identified by a higher current that flows in such stripes when the stripes are appropriately biased. From these there can be identified ones that extend just beyond the edge.
More specifically, the invention involves locating on the wafer over the surface region where there is to be formed a well whose edge is to be determined, an overlay pattern comprising a series of conductive stripes. Each stripe serves as a fixed probe to determine the conductivity of the surface region at which the buried end of it terminates. Each stripe advantageously is connected to a separate conductive pad for easy access and a multiplexing circuit is used to interconnect appropriate pairs of pads. There can be located the edge of a particular well region by subsequently applying a voltage and measuring any resulting current flow between different pairs of such stripes. A variety of overlay stripe patterns are feasible for locating either a single edge or a pair of edges of the well.
From a first apparatus aspect, the present invention is semiconductor apparatus. The semiconductor apparatus comprises a semiconductor body having a top surface and being of a first conductivity type and including an insulating layer over a portion of the top surface, a semiconductor region of a second opposite conductivity type adjacent said semiconductor body for forming a p-n junction with the semiconductor body which underlies the insulating layer, and a plurality of spaced-apart conductive stripes. The plurality of spaced-apart conductive strips each have first and second ends with the first ends at the top surface of the semiconductor body and the second ends buried under the insulating layer, and with the second end of at least one of the conductive strips making low resistance contact with the semiconductor region and at least one failing to make a low resistance contact.
From a second apparatus aspect, the present invention is semiconductor apparatus comprising a silicon wafer, an insulating layer, and a plurality of conductive stripes. The silicon wafer comprises a portion that includes at least one calibration well of the conductivity type opposite that of its surrounding region for forming a vertical p-n junction therewith. The insulating layer overlies the p-n junction. The plurality of conductive stripes extend from the top surface of the portion and have buried ends underlying partially the insulating layer for forming distinct conductive paths in said surrounding region and directed at the vertical edge of the p-n junction of which at least one conductive stripe penetrates the junction to form a conductive path to the well and at least one that falls short of the junction. At least one other conductive connection to the well for forming a conductive path through the calibration well with a penetrating stripe.
From a first method aspect, the present invention is a method for locating an edge of a semiconductor well of one conductivity that is formed in a semiconductor body of the opposite conductivity type which edge underlies an insulating layer. The method comprises the steps of: forming in the semiconductor body before the semiconductor region and the insulating layer are formed a plurality of distinct conductive stripes of each includes a first end at the top surface of the semiconductor body and a second end buried under a portion of the top surface where the insulating layer is to be formed, of which at least one conductive stripe has a second end extends across the edge and at least one second end that be short of the edge; forming an insulating layer over a portion of the top surface of the semiconductor body and covering the second ends of the stripes; forming in the semiconductor body a semiconductor well of the opposite conductivity type for forming the edge that underlies the insulating layer whose edge is to be located, said semiconductor well including the buried second ends of only some but less than all of the conductive stripes; and determining which of the stripes includes buried second ends that make low resistance connections to the semiconductor well.
From a second method aspect, the present invention is a method for determining in a semiconductor wafer an edge that is of a well of conductivity different from its surrounding region and that underlies an insulating layer that overlies the edge of the well, said method includes forming over the surface before the forming of either the insulating layer or the well an overlay pattern of spaced-apart conductive stripes that extend under the insulating layer to be formed to provide distinct conductive paths in the semiconductor wafer, of which at least one extends sufficiently to penetrate the edge of the well to be formed to provide a low resistance connection to the well after it has been formed.
From a third method aspect the present invention is a method of determining in a semiconductor wafer the location of two opposed edges that are of a well of conductivity type opposite that of the surrounding region and that underlie an insulating layer by forming over the surface of the wafer before forming of the well an overlay pattern of conductive stripes that extend under the insulating layer to be formed and that comprise a first and second set of which at least one of the first set
Mono Tobias
Schafbauer Thomas
Von Ehrenwall Andreas
Chambliss Alonzo
Lerner David Littenberg Krumholz & Mentlik LLP
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