Boots – shoes – and leggings
Patent
1977-09-20
1978-12-05
Nusbaum, Mark E.
Boots, shoes, and leggings
235304, 23530342, G06F 1100, G06F 700
Patent
active
041288734
ABSTRACT:
A structure for an easily testable single chip calculator/controller comprising an arithmetic logic unit (ALU) and a plurality of active storage elements all interconnected in parallel via an input bus and an output bus. Instructions contained in a read only memory (ROM) are read out into an instruction register. A first means is provided for decoding a portion of the instruction to generate a configuration signal for selectively configuring the logic elements of the ALU. A second means is provided for decoding the remainder of the instruction to generate a register select signal for selectively actuating a chosen storage element. Two test pins are provided, one placed in the input bus and the other placed in the output bus. The test pins are placed in the test mode by the application of a TEST signal to their terminals. Signals from the test pins will be routed to outside diagnostic or testing equipment. All the storage elements may then be read out or written via these two test points by simply decoding an instruction from the instruction register so as to cause the first decoding means to configure the ALU and the second decoding means to access a particular storage unit. The task of testing the chip is simplified since the ALU may act upon any of the storage elements via the parallel input/output bus lines.
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Burroughs Corporation
Feeney, Jr. Edward J.
Gaudier Dale V.
Nusbaum Mark E.
Peterson Kevin R.
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